Formalni postupci u oblikovanju računalnih sustava(2008) Auditorne_1: , 14:00 – 16:00, D1 Pred. (Logika) , 09:15 – 11:00B4 Auditorne_2: , 08:00-10:00D1 Test sustava: , 14:00 – 16:30A 102 Prvi lab otvoren: , 16:30 – 18:00A 102 Pred. (CTL) , 09:15 – 11:00B4 Auditorne_3: :00 – 10:00D1 Prvi lab kolokvij: , 14:00 – 16:30 A 102, 101 Za raspored po grupama vidi Web stranicu labosa

Formal verification I = Implementation (model of the system to be verified) S = Specification (behavior) Expressed in temporal logic Verifier YES NO (error trace) I  S 1.How to model I ? 2.What is 3.How to model S ?

A 1) Verifikacija sklopovlja Primjer:Arbitar sabirnice Opis implementacije (I):Verilog (HDL) Opis specifikacije (S):CTL Sustav za verifikaciju:VIS A 2) Verifikacija dijelova programskih produkata Primjeri:Međ. isključ. proc. Opis implementacije (I):SMV Opis specifikacije (S):CTL Sustav za verifikaciju:SMV

A 1) Laboratorijske vježbe iz verifikacije sklopovlja: Arbitar sabirnice (engl. Bus Arbiter) Opis implementacije ( I ): Verilog Opis specifikacije ( S ): CTL vremenska logika Sustav za verifikaciju: VIS

Verification Synthesis Simulation CTL Fairness Blif-mv VHDL Verilog SMV SIS Move around View hierarchy VIS : PASSFAIL (error trace) S = bar.ctl I = foo.v F = go.fair

Na stranicama lab. vježbi VIS dokumentacija Za implementaciju I: 1.VIS User Manual 2.Verilog – kratki opis 3.Verilog – pregled naredbi Za specifikaciju S: 1.VIS CTL Manual

VERILOG Jezik za opis sklopovlja (HDL), sintaktički posudio mnogo od C-a. Opis na više razina apstrakcije. IEEE standard # Verilog datoteke se mogu verificirati, simulirati i sintetizirati. Ref.: 1. Donald E. Thomas and Philip R. Moorby The Verilog Hardware Description Language, 4th Ed. Kluwer, (Carnagie Melon University) 2. (VERILOG i VHDL)

g1 g2 f1 f2 nsel

!!!!!

Second: temp store before assign addition (Logical OR = II)

(anything can be accessed, bad style)

same as a.e since no local e This e is different (it is top e)

e e logic only Inputs: A B C D Ex = char. “d” e = 1 (ON) CD AB

module fsm(out, in, clock, reset); outputout; inputin, clock, reset; regout; reg[1:0]currentState, nextState; // combination portion * * * // sequential portion * * * endmodule Output State Input neg. edge clock pos. edge 00/0 01/1 11/ reset

// combination portion or currentState) begin out = ~currentState[1] & currentState[0]; // out = 1 only for state 01 nextState = 0; if (currentState == 0) if(in) nextState = 1; //else stay in 0 if (currentState == 1) if (in) nextState = 3; //else go to 0 if (currentState == 3)begin if (in) nextState = 3; else nextState = 1; end // the sequential portion clock or negedge reset) begin if (~reset) currentState <= 0; // as long as res=0 else currentState <= nextState; // as D type bistable end Bit select = 01 Non blocking

Verilog extensions (in VIS environment) Enumerated types ( similar to C ) typedef enum {IDLE, READY, BUSY} controller_state; /* contr._state is an enum type */ controller_state reg state; /* state is a register variable of the type “controller_state” */

Non-determinism There exist state-input pair for which the next state and output are not unique. $ND construct creates a nondeterministic signal source should only be used in an assign statement wire r;/* def of a wire variable */ assign r=$ND(GO, NOGO);/* nondeterminism */. clk) begin. state = r; /* the state is nondeterm. GO or NOGO */. end

clientAclientBclientC Example: Arbiter

module main(clk); …// typedef …// input, output, wire, reg... controller controllerA(clk, reqA, ackA, sel, pass_tokenA, A); controller controllerB(clk, reqB, ackB, sel, pass_tokenB, B); controller controllerC(clk, reqC, ackC, sel, pass_tokenC, C); arbiter arbiter(clk, sel, active); client clientA(clk, reqA, ackA); client clientB(clk, reqB, ackB); client clientC(clk, reqC, ackC); endmodule module controller(clk, req, ack, sel, pass_token, id); input clk, req, sel, id; output ack, pass_token; …. endmodule module arbiter(clk, sel, active); input clk, active; output sel;... endmodule module client(clk, req, ack); input clk, ack; output req;... endmodule

A 2) Laboratorijske vježbe iz verifikacije programskih dijelova: Algoritmi međusobnog isključivanja procesa (mutex) Opis implementacije ( I ): SMV Opis specifikacije ( S ): CTL vremenska logika Sustav za verifikaciju: SMV

SMV - Symbolic model verifier Ken McMillan, CMU, Ph.D. thesis, Formalni model (/)- SMV sintaksa Formalna specifikacija (S)- CTL formule SMV sustav za verifikaciju S I Da / Ne (+ error trace) foo.smv

Implementacija ( I ): stroj s konačnim brojem stanja (FSM) u SMV kodu req = 0 st.=ready req = 1 st.=ready req = 1 st.=busy req = 0 st.=busy request = {0, 1} (npr. 1=True, 0=False) status = {ready, busy}

MODULE main // foo.smv file VAR request: boolean // type boolean status: {ready, busy} // type sclr {ready, busy} ASSIGN init (status) := ready; // init status value next (status) := case // next status value request : busy; // if st=rdy  req=1 in crnt state, then next st=bsy 1 : {ready, busy}; // else not det. esac; SPEC AG(request -> AF status = busy) // CTL spec.

MODULE main // ring of 3 inverters, each with diff. speed VAR gate1 : process inverter(gate3.output); gate2 : process inverter(gate1.output); gate3 : process inverter(gate2.output); // SMV chooses and runs any process module nondeterminist. // useful to describe parallel processes, e.g comm. protocols SPEC (AG AF gate1.out) & (AG AF !gate1.out) MODULE inverter(input) VAR output : boolean; ASSIGN init(output) := 0; next(ouput) := !input;// output inverts input with type chk