VHDL – Behavioral Modeling and Registered Elements ENGIN 341 – Advanced Digital Design University of Massachusetts Boston Department of Engineering Dr.

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Presentation transcript:

VHDL – Behavioral Modeling and Registered Elements ENGIN 341 – Advanced Digital Design University of Massachusetts Boston Department of Engineering Dr. Filip Cuckov

Overview 1.Processes and Behavioral Modeling 2.Processes Describing Registered Elements 3.Processes Describing State Machines

1. Processes and Behavioral Modeling Processes are VHDL constructs designed to be containers for a behavioral description of a circuit’s operation Synthesizable processes must have a sensitivity list A list of inputs that contribute to the resolution of the output Either explicit (recommended) or use wait on signal statements Statements within process are executed sequentially Signal updates are committed once the end process clause has been reached Variable updates are committed immediately after their assignment within a process

Dataflow vs. Process VS.

Combinatorial vs. Sequential Circuits Processes that describe combinatorial logic are sensitive to every input that contributes to the resolution of an output Processes that describe sequential circuits are sensitive to clock (CLK) Possibly a reset (RST), clock enable (CE), and other inputs depending on the physical mapping to a registered element that is to be inferred. Source: ug953-vivado-7series-libraries.pdf

2. Processes Describing Registered Elements

Example: Toggler

One Counter Testbench Cascaded Counters Testbench