© 2003 Xilinx, Inc. All Rights Reserved Course Wrap Up DSP Design Flow.

Slides:



Advertisements
Similar presentations
© 2003 Xilinx, Inc. All Rights Reserved Course Wrap Up DSP Design Flow.
Advertisements

Developing Video Applications on Xilinx FPGAs
Integrated Circuits Laboratory Faculty of Engineering Digital Design Flow Using Mentor Graphics Tools Presented by: Sameh Assem Ibrahim 16-October-2003.
© 2003 Xilinx, Inc. All Rights Reserved Looking Under the Hood.
MotoHawk Training Model-Based Design of Embedded Systems.
Midterm Project Presentation Bandpass Filter on FPGA Student Vitaly Zakharenko Supervisor Mony Orbach Semester Spring 2007 Duration single semester.
1 Performed By: Khaskin Luba Einhorn Raziel Einhorn Raziel Instructor: Rivkin Ina Spring 2004 Spring 2004 Virtex II-Pro Dynamical Test Application Part.
Aug. 24, 2007ELEC 5200/6200 Project1 Computer Design Project ELEC 5200/6200-Computer Architecture and Design Fall 2007 Vishwani D. Agrawal James J.Danaher.
Configurable System-on-Chip: Xilinx EDK
VHDL Synthesis in FPGA By Zhonghai Shi February 24, 1998 School of EECS, Ohio University.
FPGA BASED IMAGE PROCESSING Texas A&M University / Prairie View A&M University Over the past few decades, the improvements from machine language to objected.
CSCE 491: Capstone Computer System Project Instructor: Jason D. Bakos.
Coordinate Based Tracking System
Railway Foundation Electronic, Electrical and Processor Engineering.
Tejas Bhatt and Dennis McCain Hardware Prototype Group, NRC/Dallas Matlab as a Development Environment for FPGA Design Tejas Bhatt June 16, 2005.
George Mason University ECE 448 – FPGA and ASIC Design with VHDL Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts,
Implementation of DSP Algorithm on SoC. Mid-Semester Presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompaning engineer : Emilia Burlak.
Railway Foundation Electronic, Electrical and Processor Engineering.
v8.2 System Generator Audio Quick Start
© 2003 Xilinx, Inc. All Rights Reserved Multi-rate Systems.
GallagherP188/MAPLD20041 Accelerating DSP Algorithms Using FPGAs Sean Gallagher DSP Specialist Xilinx Inc.
GPGPU platforms GP - General Purpose computation using GPU
FPGA Based Fuzzy Logic Controller for Semi- Active Suspensions Aws Abu-Khudhair.
© 2011 Xilinx, Inc. All Rights Reserved Intro to System Generator This material exempt per Department of Commerce license exception TSU.
Delevopment Tools Beyond HDL
Image Processing for Remote Sensing Matthew E. Nelson Joseph Coleman.
StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to:  Describe how.
Simulink ® Interface Course 13 Active-HDL Interfaces.
Highest Performance Programmable DSP Solution September 17, 2015.
DSP Design Flows in FPGA
Introduction to Design Tools COE Review: Tools, functions, design flow Four tools we will use in this course – HDL Designer Suite FPGA Advantage.
Digital Radio Receiver Amit Mane System Engineer.
RM2D Let’s write our FIRST basic SPIN program!. The Labs that follow in this Module are designed to teach the following; Turn an LED on – assigning I/O.
Simulink ® Interface Course 13 Active-HDL Interfaces.
© 2003 Xilinx, Inc. All Rights Reserved Advanced Features.
© 2003 Xilinx, Inc. All Rights Reserved Answers DSP Design Flow.
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Xilinx Design Flow FPGA Design Flow Workshop.
© 2003 Xilinx, Inc. All Rights Reserved HDL Co-Simulation.
© 2003 Xilinx, Inc. All Rights Reserved DSP Design Flows in FPGA.
FPGA (Field Programmable Gate Array): CLBs, Slices, and LUTs Each configurable logic block (CLB) in Spartan-6 FPGAs consists of two slices, arranged side-by-side.
Senior Project Presentation: Designers: Shreya Prasad & Heather Smith Advisor: Dr. Vinod Prasad May 6th, 2003 Internal Hardware Design of a Microcontroller.
Introduction to FPGA Created & Presented By Ali Masoudi For Advanced Digital Communication Lab (ADC-Lab) At Isfahan University Of technology (IUT) Department.
This material exempt per Department of Commerce license exception TSU Multi-rate Systems.
© 2011 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU DSP Design Flow System Generator for DSP.
Part A Presentation Implementation of DSP Algorithm on SoC Student : Einat Tevel Supervisor : Isaschar Walter Accompanying engineer : Emilia Burlak The.
ECE 545 Project 2 Specification. Schedule of Projects (1) Project 1 RTL design for FPGAs (20 points) Due date: Tuesday, November 22, midnight (firm) Checkpoints:
Programmable Logic Training Course HDL Editor
© 2003 Xilinx, Inc. All Rights Reserved System Simulation.
Introductory project. Development systems Design Entry –Foundation ISE –Third party tools Mentor Graphics: FPGA Advantage Celoxica: DK Design Suite Design.
© 2005 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU HDL Co-Simulation.
ECE-C662 Lecture 2 Prawat Nagvajara
Tools - LogiBLOX - Chapter 5 slide 1 FPGA Tools Course The LogiBLOX GUI and the Core Generator LogiBLOX L BX.
CORE Generator System V3.1i
ESS | FPGA for Dummies | | Maurizio Donna FPGA for Dummies Basic FPGA architecture.
Graphical Design Environment for a Reconfigurable Processor IAmE Abstract The Field Programmable Processor Array (FPPA) is a new reconfigurable architecture.
© 2003 Xilinx, Inc. All Rights Reserved Answers DSP Design Flow.
Teaching Digital Logic courses with Altera Technology
Basic Xilinx Design Capture. © 2006 Xilinx, Inc. All Rights Reserved Basic Xilinx Design Capture After completing this module, you will be able.
Programmable Logic Devices
Implementing Combinational
Introduction to Programmable Logic
Introduction Introduction to VHDL Entities Signals Data & Scalar Types
Course Agenda DSP Design Flow.
A Comparison of Field Programmable Gate
Matlab as a Development Environment for FPGA Design
ECE-C662 Introduction to Behavioral Synthesis Knapp Text Ch
VHDL Introduction.
THE ECE 554 XILINX DESIGN PROCESS
ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL code ECE 448 – FPGA and ASIC Design.
THE ECE 554 XILINX DESIGN PROCESS
Presentation transcript:

© 2003 Xilinx, Inc. All Rights Reserved Course Wrap Up DSP Design Flow

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 1 Describe why parallelism enables high performance Describe the Virtex™-II, Virtex-II Pro™, and Spartan™-3 family architectural resources that are useful for DSP functions How do Xilinx FPGAs lend to an optimum implementation of DSP functions?

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 1: Answers Describe why FPGA enables high performance –Flexibility of parallel execution of basic functions due to uniform architectural resources –Tailoring to desired bit-width –Ease of applying varying sample rates Describe the Virtex™-II, Virtex-II Pro™, and Spartan™-3 family architectural resources that are useful for DSP functions –SRL16E –Distributed RAM –Block RAM –Embedded multipliers –Abundant logic and register resources

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 1: Answers How do Xilinx FPGAs lend to an optimum implementation of DSP functions? –SRL16E: storing samples when number of taps is small; implementing serial distributed arithmetic technique-based filters –Distributed RAM: To hold samples and coefficients in case of small filters; works efficiently when number of taps is in multiples of 16 –Block RAM: Suitable for storing large number of coefficients and samples –Embedded multipliers: suitable for applications that use multipliers with adjacent block RAM

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 2 Describe the advantages and disadvantages of three different design flows Describe the System Generator and the tools it interfaces with Describe steps involved in the Hardware in the Loop verification

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 2: Answers Describe the advantages and disadvantages of three different design flows –VHDL based designs Advantages: Portability, complete control of the design implementation and tradeoffs, easier to debug Disadvantages: Time-consuming, need to be familiar with the algorithm and how to write it, must be conversant with the synthesis tools to obtain optimized design –CORE Generator based designs Advantages: Quick access to existing functions, IP is optimized for the specified architecture Disadvantages: May not have exact functionality –System Generator based design Advantages: High productivity, ability to simulate at a system level, very attractive for FPGA novices, hardware in the loop simulation improves productivity and accelerates verification Disadvantages: Doesn’t always give the best result from an area usage point of view, not well suited to multiple clock designs, no bi-directional bus supported

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 2: Answers Describe the System Generator and the tools it interfaces with –The System Generator is a toolbox running under the Simulink environment that provides an integrated design flow by leveraging existing technologies such as HDL synthesis, IP Core libraries, and FPGA implementation tools. It provides a simple push-button flow for HDL Co-simulation and Hardware in the Loop acceleration verification capabilities Describe the Hardware in the Loop and the steps involved in the verification –Hardware in the Loop is a Simulink hardware accelerator, which enables design verification in hardware. It is a Simulink-to-bitstream-to-Simulink push button flow to simulate HDL and EDIF-based design –Three simple steps Insert a compilation block from the vendor library into the user model Compile (Generate) the design for the co-simulation Copy a co-simulation run-time block into the user model

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 3 State some of the digital filter blocks supported in System Generator Describe the factors that will determine the digital filter implementation Describe the integration of FDATool block in System Generator

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 3: Answers State some of the digital filter blocks supported in System Generator –FIR block –CIC block Describe the factors that will determine the digital filter implementation –Sample rate –Sample width –Coefficients profile –Clock rate Describe the integration of FDATool block in System Generator –The Xilinx FDATool (Filter Design and Analysis Tool) block provides an interface to the FDATool software available as part of the MATLAB Signal Processing Toolbox. It provides a powerful means for defining digital filters with a graphical user interface and storing it as part of a System Generator model

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 4 Why HDL Co-simulation? Name supported blocks for the HDL Co-simulation State the steps involved in performing the HDL Co-simulation

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 4: Answers Why HDL Co-simulation? –It provides designers a means to incorporate legacy code in a Simulink-based system DSP design –Legacy code can be simulated in Simulink to significantly reduce development time Name supported blocks for the HDL Co-simulation –Black Box –Simulation Multiplexer –ModelSim State the steps involved in performing the HDL Co-simulation –Drag a Black Box block in a design and assign the legacy code to it –Drag a ModelSim block into the design and select ModelSim simulation mode –Run the Simulink simulation, which will open the ModelSim simulator

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 5 What is quantization? Why does it occur? State the two options available to handle it? What is an overflow? Why does it occur? State the three options available to handle it? Why do we need bit picking? State the four blocks available for this purpose?

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 5: Answers What is quantization? Why does it occur? State the two options available to handle it? –Quantization is a process of handling higher-precision number representation with a lower-precision number representation –In Simulink the numbers are represented in double-precision whereas in Xilinx Blockset, the numbers are represented in fixed-point –Truncate and Rounding are the two options available to handle it What is an overflow? Why does it occur? State the three options available to handle it? –An overflow occurs when a large number is represented in a smaller range representation –In Simulink, the numbers are represented in double-precision whereas in Xilinx Blockset, the numbers are represented in fixed-point –Saturate, Wrap the value, and Flag an error are the three options available

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 5: Answers Why do we need bit picking? State the four blocks available for this purpose? –There may be a need to Combine two data buses together to form a new bus Force a conversion of data type including the number of bits and binary bits Reinterpret unsigned data as signed, or the converse Extract certain bits of data, especially when there is bit growth –The four blocks available are Concat Convert Reinterpret Slice

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 6 Describe the control mechanisms available in System Generator State the available blocks in System Generator to control data movement

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 6: Answers Describe the control mechanisms available in System Generator –There are two mechanisms available in System Generator to control the data flow Enable ports Reset ports –Enable port, if available, is connected to a signal that is asserted at a multiple of the block 's sample rate and must be of Boolean type –Reset port, if available, is connected to a signal that is when asserted places the block in its initial state. The signal must be of Boolean type State the available blocks in System Generator to control data movement –MCode block –Expression block –Mealy State Machine block –Moore State Machine block

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 7 Define multi-channel and multi-rate systems State sample rate changing blocks Describe Simulink propagation rules

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 7: Answers Define multi-channel and multi-rate systems –A system is said to have multiple channels when same datapath processing is taking place in parallel –Multi-rate systems are those that have varying sampling rates needs State sample rate changing blocks –Up Sample –Down Sample –Parallel to Serial –Serial to Parallel

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 7: Answers Describe Simulink propagation rules –All blocks inherit their input sample rate –SysGen idiom: “explicit inherited” sample period tells Simulink to inherit first encountered sample time –Feedback loops cause problems for Simulink’s propagation algorithms Must set at least one explicit sample time in every feedback loop

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 8 How would you design a system using multiple FPGAs in Simulink? Why parametric designs and how would you create such designs? Describe the steps involved to enable switching between multiple System Generator versions? State the design flow associated with the PicoBlaze™ microcontroller

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 8: Answers How would you design a system using multiple FPGAs in Simulink? –Create a top-level design (should not have System Generator tokens including Gateway In and Gateway Out) with multiple sub-systems –For each sub-system, include Gateway In, Gateway Out, and System Generator token –For each sub-system, generate the design for the desired device family and part Why parametric designs and how would you create such designs? –Provides flexibility of changing parameters and hence the same block can be used at different places in a design with different parameters –Create a sub-system with relevant parameters –Using functions like get_param, set_param, find_system, add_block, delete_block add_line, delete_line, etc.

Wrap up: DSP Design Flow © 2003 Xilinx, Inc. All Rights Reserved Module 8: Answers Describe the steps involved to enable switching between multiple System Generator versions? –Edit the instlist.txt file located in each version installation directory (e.g., $MATLAB \toolbox\xilinx2_3\sysgen\util) to include various installed versions, for example 2.3 C:/MATLAB6p1/toolbox/xilinx2_3/sysgen 3.1 C:/MATLAB6p1/toolbox/xilinx/sysgen –To activate use xlversion command with version number in the Matlab command window State the design flow associated with the PicoBlaze™ microcontroller –Create a program file –Run the compiler –Assign the program file (assembled output file *.m) to the instruction ROM