1 J.M. Heuser − STS Development Microstrip detector GSI-CIS Johann M. Heuser, GSI Li Long, CIS CBM Collaboration Meeting, GSI, 27.2.2008 Update on.

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Presentation transcript:

1 J.M. Heuser − STS Development Microstrip detector GSI-CIS Johann M. Heuser, GSI Li Long, CIS CBM Collaboration Meeting, GSI, Update on ongoing and launched activities

2 J.M. Heuser − STS Development tracking station with readout electronics outside of the aperture 2 projective coordinates, if possible in one thin silicon layer: double-sided strip detector electrical contacts at sensor's top/bottom edge: ladder construction no "dead" region in the corners, despite of strips oriented under a stereo angle. high radiation tolerance: design, material 1 st R&D study GSI-CIS: "CBM01" - focus on connectivity Double-sided detector, with double-metal connections of strips in the corner regions contact pad rows at top and bottom edge. Technical challenge CBM STS tracking station Detector module readout direction p side "double metal" blue: double metal connections of strips I to III n side: "vertical" strips I II III

3 J.M. Heuser − STS Development Microstrip detector prototype CBM01, 8/2007 4" wafer, 285 µm Si Test sensors Double-sided, double-metal, 1024 strips per side, 50 µm pitch, 15º stereo angle, full-area sensitive, contacts at top + bottom edge, size: 56  56 mm 2 Double-sided, single-metal, 256  256 strips, orthogonal, 50(80) µm pitch, size: 14  14 (22  22) mm 2 Main sensor

4 J.M. Heuser − STS Development Characterization at CIS IV and CV behaviour of CBM01B1, CBM01B2, CBM02 (Mr. John et al.) reported at CBM Meeting September 2007 U [V] I [µA] U[V] I [µA] U [V] 1/C 2 [pF - 2 ]

5 J.M. Heuser − STS Development Find application in various activities of beginning detector module R&D Only available CBM-specific microstrip detectors GSI: Test board (CBM01B2, preparation, report A. Lymanets) Test beam tracking module (planned) KINR Kiev: Pre-prototype module & CBM01B1 detector tests (electrical, diode laser, radioactive source) (report V. Pugatch) Kharkov: Test board with microcable fanout structure (planned) Cracow: n-XYTER-SUCIMA board with CBM01B2 (planned) + many new ideas ooooooooo

6 J.M. Heuser − STS Development Towards 2 nd design iteration CIS activity in frame of german BMWI project INNOWAT -“SPID“: Test wafer to explore primarily radiation tolerance Bias method: punch-through, poly-silicon Breakdown voltage: charge, micro discharge Insulation technology: p-spray, p-stop, field plate

7 J.M. Heuser − STS Development Full detectors 7 pixel detectors; 18 strip detectors. Test structures: 3 Pad diodes, 4 Gate diodes, 6 PDTF, 2 SIMS, 2 SDM. Process status 2/2008: First active implant finished. Second manufacture run ("technology wafer") L. Long and R. Rolf, CIS

8 J.M. Heuser − STS Development ohmic side Simulation of electrical properties Layout calculation: coupling capacitance front21 pF/cm coupling capacitance back15 pF/cm resistance for front metal 25 Ohm/cm resistance for back metal 16 Ohm/cm resistance for cross connection 28 Ohm/cm Technology simulation: resistance for p front66 kOhm/cm resistance for n back44 kOhm/cm junction side Electrical field:

9 J.M. Heuser − STS Development WaferPolyp-Stopp-SprayPoly (1 MOhm) 1XX 3,5e12,115keV 2X 1.5MOhm 3XX 3,2e12, 115keV 4X 1.5MOhm 5XX 4,0e12, 115keV 6X 1.5MOhm 7XX 5e12, 80keV 8X 9XX 1.1e13 70keVX 3,5e12,115keV 10XX 2e13 70keVX 3,5e12,115keV 11XX 1.1e13 70keV 12XX 2e13 70keV 13X 1.1e13 70keVX 3,5e12,115keV 14X 2e13 70keVX 3,5e12,115keV 15X 1.1e13 70keV 16X 2 e13 70keV 17X 3,5e12,115keV 18X 3,5e12,115keV Technology variations in detail (I) Wafers with different processing

10 J.M. Heuser − STS Development NameQuantitybiasingisolationpitchGuard Twpx11, PixelPunchSpray80*120No Twpx31, PixelPunchSpray80*120Guard Twsp52,stripPunchSpray80Guard Twsp61,stripPunchSpray50Guard mastercis5, PixelPunchSprayGuard Cap_gcdiode_ntestfeld2Test structure Cap_gcdiode_ptestfeld2Test structure Diode1_ptestfel_1Test structure Diode2_ptestfeld1Test structure Diode3_ptestfeld1Test strckture PDTF02st1Test structure PDTF02nn1Test structure PDTF02n1Test structure PDTF02p1Test structure PDTF02pn1Test structure PDTF02pp1Test structure Technology variations in detail (II) Detectors and test structures on the wafers

11 J.M. Heuser − STS Development NameQuantitybiasingisolationpitchGuard sdm2Test structure Sims12Test structure Twpsp151,stripPolySpray80,48Guard Twpsp121,strippunchSpray80Guard Twpsp131,stripPoly+punchPstop+ Spray80Guard Twpsp141,strippunchSpray80Guard Twpsp21,stripPolySpray50Guard Twpsp221,strippunchSpray50Guard Twpsp231,strippoly+punchPstop+ Spray50Guard Twpsp241,strippoly+punchPlate+ Spray50Guard Twpsp251,strippunchSpray502xguard Twpsp51,stripPoly+punchSpray80No Twpsp61,strippoly+punchSpray50No Twpsp71,stripPunchSprayw/pGuard Twpspg52,strippoly+punchSpray80 w/pGuard Twpspg61,strippoly+punchSpray50 w/pGuard Technology variations in detail (III) Detectors and test structures on the wafers

12 J.M. Heuser − STS Development 1.The designed poly resistors has 230 squares, the sheet resist should be 4.3k  /Sq by 1M  and 6.5k  /Sq by 1.5M . 2.For Test wafer we need only two masks. 3.Flow card for poly-resist test: Processing steps: LTO deposition Poly-Silicon deposition Oxidation. Implantation Boron variations Removing of oxid Photolithography and patterning Aluminium 1µm Photolithography and patterning Polysilicon bias structures  New at CIS.

13 J.M. Heuser − STS Development L. Long, CiS Erfurt, Requirement of n-XYTER front end to the inter strip capacitance of the CBM01 detector: It seems that Ctotal (Ccable + Cint_detector+ Cin_n-XYTER) ~< 30pF. Cint = capacitance of one strip against the two neighbour strips connected together, at frequency 10kHz and 100kHz. Rint = resistance of one strip against the two neighbour strips connected together. Both of them are tested at full depletion condition. Comparison between CBM01 and ALICE microstrip detector: Length [µm] Pitch [µm] Width [µm] Cint [pF] Rint [G  ] ALICE CBM Interstrip capacitance of the CBM01 detector

14 J.M. Heuser − STS Development Electrical simulations, r/o cable Cij Simple model: Five strip lines are considered. Middle strip 1V, all other strips 0V. Inter-strip capacitance: 2 × 0.4 = 0.8 pF/cm.  noise load for FE electronics. (L. Long, CIS)

15 J.M. Heuser − STS Development Signal-to-noise in a detector system Cable: ~0.8 pF/cm Sensor: typically 1.5 pF/cm strip n-XYTER: ENC26.9 e/pF e (fast channel) 12.7 e/pF e (slow channel) Signal in 280 µm Si:80 e/µm × 280 µm = e Let‘s assume an average detector module: 6cm strip + 30 cm cable: C interstrip = 35 pF → n-XYTER will see 35 pF = 1100 e S/N ( e) = 20 S/N ( e, charge shared by 2 strips) = 10 on the edge ? Simple exercise: (J. Heuser)

16 J.M. Heuser − STS Development Cooperation GSI-CiS on microstrip detector development and production for CBM is very effective. First detector prototypes CBM01 have been fabricated in 2007 after an intensive, innovative preparation phase in Extremely useful now for STS prototyping. Many teams depend on these detectors for the R&D tasks. Currently under production: "Technology wafer" for improved next version of the CBM microstrip detectors. Prime target: Radiation hardness. Next full detector design: Will probably take some time, first need evaluation from 1 st wafer and from "technology" wafer, CBM needs to specify its further requirements. Next project with CiS involvement: Single-sided strip detectors? Summary/Outlook

17 J.M. Heuser − STS Development ALICE & ATLAS industry awards to CiS CIS has been subcontractor of Canberra for the ALICE microstrip detectors. Cern made the specification, Canberra made the design, CiS made the whole processing. In 2006, the ALICE detectors from CiS received an award from CERN (through CANBERRA).