Tom McMullen Week 7 18/3/2013 – 22/3/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.

Slides:



Advertisements
Similar presentations
Silicon Technical Specifications Review General Properties Geometrical Specifications Technology Specifications –Mask –Test Structures –Mechanical –Electrical.
Advertisements

ASE Flip-Chip Build-up Substrate Design Rules
Center for Materials and Electronic Technologies
ECFA-DESY meeting, Krakow, 16 th September 2001Václav Vrba, Institute of Physics, AS CR 1 Václav Vrba Institute of Physics AS CR, Prague Silicon pad sensors.
Hybridization studies at Fermilab Prototype detectors –Readout chip mated to sensor –Experiences with both single dies and 4” and 6” wafers using Indium.
Bump bonding follow up from AUW R. Bates & F. Hügging.
UK – quad module. Experience with FE-I4 UK groups relatively new to ATLAS pixel Have 5 USBPix systems up and running now – Glasgow, Edinburgh, Manchester,
General needs at CERN for special PCB’s Philippe Farthouat CERN.
3D PACKAGING SOLUTIONS FOR FUTURE PIXEL DETECTORS Timo Tick – CERN
WP6 interconnect technology part
Tom McMullen Week 5 4/3/2013 – 8/3/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.
Tom McMullen Week 9 1/4/2013 – 5/4/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.
Tom McMullen Week 6 11/3/2013 – 15/3/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.
Tom McMullen Week 3 25/2/2013 – 1/3/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.
20th RD50 Workshop (Bari)1 G. PellegriniInstituto de Microelectrónica de Barcelona G. Pellegrini, C. Fleta, M. Lozano, D. Quirion, Ivan Vila, F. Muñoz.
Status and outlook of the Medipix3 TSV project
3D chip and sensor Status of the VICTOR chip and associated sensor Bonding and interconnect of chip and sensor Input on sensor design and interconnection.
Plans for Demonstrator Flip Chip Bonding GTK meeting 9/12/08 1.
J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Flip Chip/Bumping Process at VTT Last modified March 16, 2007 By Jaakko.
WP7&8 Progress Report ITS Plenary meeting, 23 April 2014 LG, PK, VM, JR Objectives 2014 and current status.
St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 1 Václav Vrba Institute of Physics, AS CR, Prague Silicon pad sensors for W-Si ECal.
Tom McMullen Week 3 18/2/2013 – 22/2/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.
March 20, 2001M. Garcia-Sciveres - US ATLAS DOE/NSF Review1 M. Garcia-Sciveres LBNL & Module Assembly & Module Assembly WBS Hybrids Hybrids WBS.
1 Moore’s Law – the Z dimension Sergey Savastiouk, Ph.D. April 12, 2001.
Tom McMullen Weeks 1 and 2 4/2/2013 – 15/2/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.
Sensor and ladder and dimensions dateChangeVersionwho 3/26/2013Updated with U2 fid positions 1.1LG.
Fabian Hügging – University of Bonn – February WP3: Post processing and 3D Interconnection M. Barbero, L. Gonella, F. Hügging, H. Krüger and.
G. Parès – A. Berthelot CEA-Leti-Minatec GU project status.
Tracker Upgrade Week –Sensors Meeting Sensor Production 24. July 2014 Marko Dragicevic.
Hybrid Integrated Circuit
From hybrids pixels to smart vertex detectors using 3D technologies 3D microelectronics technologies for trackers.
Sensor (0,0) (20235, 22725) PXL Ultimate sensor Diced Silicon Size mm x mm There is a uniform 15 um border around the sensor lithography 15.
CERN Rui de OliveiraTS-DEM TS-DEM Development of Electronic Modules Rui de Oliveira CERN CERN hybrid production experience (or how to stay out of trouble)
Update on tendering for HIC automatic assembly system A. Di Mauro ITS Upgrade Plenary,
P. Riedler- GGT Meeting 3/4/20061 Status of Sensor Irradiation and Bump Bonding P. Riedler, G. Stefanini P. Dalpiaz, M. Fiorini, F. Petrucci.
Dummy and Pad Chips Needed for various activities (interconnection tests, mass tests, assembly,…) Production of masks, processing, thinning and dicing.
Tom McMullen Period 3 Week 9 8/4/2013 – 12/4/2013.
Estimated schedule, costs and number of ABC130 needed Tony Affolder.
Foundry Characteristics
DESIGN CONSIDERATIONS FOR CLICPIX2 AND STATUS REPORT ON THE TSV PROJECT Pierpaolo Valerio 1.
Low Mass Rui de Oliveira (CERN) July
Sensor testing and validation plans for Phase-1 and Ultimate IPHC_HFT 06/15/ LG1.
Roadmap to the next 2015 run F. Marchetto GigaTracKer Working Group meeting Dec. 9 th 2014 a)Introductory meeting on Nov. 27, 2014 b)At that meeting several.
Tom McMullen Week 8 25/3/2013 – 29/3/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.
D. Henry / CEA-Leti-Minatec Contibuting authors : A. Berthelot (LETI) / R. Cuchet (LETI) / J. Alozy (CERN) / M. Campbell (CERN) AIDA Meeting / 08 & 09th.
MEMS Packaging ד " ר דן סתר תכן וייצור התקנים מיקרומכניים.
Phase 2 Tracker Meeting 6/19/2014 Ron Lipton
L. Greiner1IPHC-LBNL Phone Conference 07/10/2012 STAR IPHC-LBNL Phone Conference News and updated ladder testing.
Giulio Pellegrini 27th RD50 Workshop (CERN) 2-4 December 2015 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona 1 Status of.
ASE ASE Flip-Chip Laminate Substrate Design ASE Flip-Chip Laminate Substrate Design Date : 07/15/03 Rev. H.
G. Ruggiero / TOTEM 1 Si Edgeless Detectors in the RPs Edgeless detector (on the old “AP25 module”) active edges (“planar/3D”) planar tech. with CTS (Current.
1ICC Proprietary MEMS DEVICE WAFER LEVEL PACKAGING TECHNICAL PRESENTATION Customer Device Wafer.
Status report Pillar-1: Technology. The “Helmholtz-Cube” Vertically Integrated Detector Technology Replace standard sensor with: 3D and edgeless sensors,
The medipix3 TSV project
SOI for Belle II PXD DEPFET Meeting, Bonn, February Ladislav Andricek, MPI für Physik, HLL  update on thinning  samples for thermal mock-ups 
Sensors Pixel dimension 300 x 300 μm2 Standard p-in-n sensors
Study of Indium bumps for the ATLAS pixel detector
New Mask and vendor for 3D detectors
Hybrid Pixel R&D and Interconnect Technologies
Alternative process flows for reduction of steps
Highlights of Atlas Upgrade Week, March 2011
Sensor Wafer: Final Layout
Micro-cooling devices for LHCb Velo CERN
Development of thin pixel modules using novel 3D Processing techniques 9th Trento Workshop, Genoa 2014 T.McMullen1, G.Pares2, L.Vignoud2, R.Bates1, C.Buttar1.
CERN & LAL contribution to AIDA2020 WP4 on interconnections: Pixel module integration using TSVs and direct laser soldering Malte Backhaus, Michael Campbell,
Report from CNM activities
SIT AND FTD DESIGN FOR ILD
SCUBA-2 Detector Technology Development
Codification of Flip Chip Knowledge
UCSB Dicing, Wire-Bonding and Board Assembly
Presentation transcript:

Tom McMullen Week 7 18/3/2013 – 22/3/2013

LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr 1.0Thin Wafer AssembliesT. McMullen01-Feb30-Sep Week 1Week 2Week 3Week 4Week 5Week 6Week 7Week 8Week PHASE 1 - Layout and mask production, first 2 wafers with microbumps delivered to AdvacamLETI - 3D101-Feb29-Mar LETI accpets CERN proposal 1.1.1Send gds to LETIT. McMullen51-Feb8-Feb Send 2 FEI4b wafers to LETIR. Bates51-Feb6-Feb Confirm step size on wafer and centre ofset variation on waferLETI51-Feb6-Feb Layout and mask productionLETI101-Feb11-Feb Deliverable 1: Microbumb gds files First 2 wafers with micro bumps delivered to AdvacamLETI4912-Feb2-Apr Deliverable 2: First 2 wafers with micro bumps delivered to Advacam Current Deliverable Target not met

Action List Phase 1 and 2 ActionWhatWhoWhenComment 6Further funding for flip-chip processRbates\Cbuttar31/3/2013Richard has confirmed this is all in place 7Bow measurement set-upTMcM31/2/2013 Tool is down and negotiations are ongoing. We may need to find an alternative 8Sensors for flip chippingAll31/3/2013Sensor availablilty for flip-chip process - Meeting rqd 9Assembly probe test solutionTMcM19/3/2013Pobe test solution for flip-chipped assemblies - yield maps 10FEI4B probe card and probe set-upRbates/TMcM19/3/2013FEI4B test solution for assembly testing yeild maps 11Experience with FEI4A probe card set-upRbates/TMcM19/3/2013FEI4A probe card set-up and testing of assemblies on Wentworth 12Source other suppliers of wafer bow measurementsTMcM29/3/2013FEI4A probe card set-up and testing of assemblies on Wentworth

Highlights and issues  Bump gds design completed and mask delivery due end of next week LETI are confident they will have delivered wafers to ADVACAM by deliverable date.  Meeting required to discuss sensor availability for the flip-chip process Amount of sensors for flip-chipping – good statistical analysis required for micro-bump yield – Richard and I have begun discussions on this. IBL TDR bump spec: ○ Pitch = 50um ○ Bump density = 26,880 per ROIC ○ Defect rate < ○ ROIC thickness <200um FEI4b Assembly testing ○ FEI4b probe card required ○ Test equipment/apparatus required ○ Semi-auto testing solution required for assemblies  Meeting set with LETI for an update 25/3/13 Project will be lead by the new 3D manager Meeting to ensure all deliverables are understood Some technical discussions around technology run 2 ○ Grinding and polishing of the wafer backside ○ Discussion around whether LETI debonds the first thinning run or we do for the thermal cycling measurements.

Highlights and issues (Cont’d)  SMC FSM thermal cycling tool is out of use at the moment. I have given them dates for when the tool is needed and asked for assurance that the tool will be ready by this time. Feedback from SMC is that they hope to have the tool running for when we require it, but have given no guarantees as yet. Sourcing alternatives ○ Southampton only have this ability to 150mm ○ JEMFIRE is another possiblity  Masks delivered to LETI and fist 2 wafers for flip-chip with micr-pillars should be available on time.

Wafer Inventory Wafer #Wafer IDYield (60 chips max)PurposeComment 1VMB8WDHG= 34, y=17, R=8, B=1Full thickness micro-bump testDelivered to LETI. High-yielding die. Micro-bump yeild testing on assemblies 2V6B8WUHG= 43, y=13, R=4, B=0Full thickness micro-bump testDelivered to LETI. High-yielding die. Micro-bump yeild testing on assemblies 3VUAYCRH First technology run. Run 2 Received at Glasgow Wafer thinning to 100microns. Used for thermal cycling bow measurements at SMC. Ship to LETI. Shipped to LETI 4ABPJXGHG=28, Y=24, R=8 First technology run. Run 2 Received at Glasgow Wafer thinning to 100microns. Used for thermal cycling bow measurements at SMC. Ship to LETI. Shipped to LETI 5 Second technology run. Run 3Wafer to be identified and delivered to glasgow 6 Second technology run. Run 3Wafer to be identified and delivered to glasgow 7 Third technology run. Run 4Wafer to be identified and delivered to glasgow 8 Third technology run. Run 4Wafer to be identified and delivered to glasgow 9 Forth technology run. Run 5Wafer to be identified and delivered to glasgow 10 Forth technology run. Run 5Wafer to be identified and delivered to glasgow

Design proposal - Microbumps schape : round shape (32 sides) instead of octogon - Electrical Continuity test proposed -Sacrified dies for alignment Bottom right corner Bottom left corner Proposed tests structures : -Only on 2 alignment chips - 2 Microbumps with 50µm diameter on each metal pad  2 pads on bottom left & 2 pads on bottom right -Test will be done directly on microbumps with microtips Proposed tests structures : -B – pad array will be use for continuity checks for contact between Cu pillars and aluminium pads. This will not affect the functionality of the chip.

LETI wafer thinning project flow Phase 2