Caltech CS184 Winter DeHon CS184: Computer Architecture (Structure and Organization) Day 1: January 6, 2003 Introduction and Overview

Caltech CS184 Winter DeHon Today Matter Computes Architecture Matters This Course (short) Who am I? Where did I come from? What do I want? Unique Nature of This Course Relation to other courses More on this course

Caltech CS184 Winter DeHon Review: Two Universality Facts Turing Machine is Universal –We can implement any computable function with a TM –We can build a single TM which can be programmed to implement any computable function NAND gate Universality –We can implement any computation by interconnecting a sufficiently large network of NAND gates

Caltech CS184 Winter DeHon Review: Matter Computes We can build NAND gates out of: –transistors (semicondutor devices) physical laws of electron conduction –mechanical switches basic physical mechanics –protein binding / promotion / inhibition Basic biochemical reactions – …many other things

Caltech CS184 Winter DeHon Starting Point Given sufficient raw materials: –can implement any computable function Our goal in computer architecture –is not to figure out how to compute new things –rather, it is an engineering problem

Caltech CS184 Winter DeHon Engineering Problem Implement a computation: –with least resources (in fixed resources) with least cost –in least time (in fixed time) –with least energy Optimization problem –how do we do it best?

Caltech CS184 Winter DeHon Quote “An Engineer can do for a dime what everyone else can do for a dollar.”

Caltech CS184 Winter DeHon Architecture Matters? How much difference is there between architectures? How badly can I be wrong in implementing/picking the wrong architecture? How efficient is the IA-32, IA-64? –Is there much room to do better? Is architecture done? A solved problem?

Caltech CS184 Winter DeHon Peak Computational Densities from Model Small slice of space –only 2 parameters 100  density across Large difference in peak densities –large design space!

Caltech CS184 Winter DeHon Yielded Efficiency Large variation in yielded density –large design space! FPGA (c=w=1) “Processor” (c=1024, w=64)

Caltech CS184 Winter DeHon Architecture Not Done Many ways, not fully understood –design space –requirements of computation –limits on requirements, density... …and the costs are changing –optimal solutions change –creating new challenges and opportunities

Caltech CS184 Winter DeHon Architecture Not Done Not here to just teach you the forms which are already understood –(though, will do that and give you a strong understanding of their strengths and weaknesses) Goal: enable you to design and synthesize new and better architectures

Caltech CS184 Winter DeHon This Course (short) How to organize computations Requirements Design space Characteristics of computations Building blocks –compute, interconnect, retiming, instructions, control Comparisons, limits, tradeoffs

Caltech CS184 Winter DeHon This Course Sort out: –Custom, RISC, SIMD, Vector, VLIW, Multithreaded, Superscalar, EPIC, MIMD, FPGA Basis for design and analysis Techniques [more detail at end]

Caltech CS184 Winter DeHon Graduate Class Assume you are here to learn –Motivated –Mature –Not just doing minimal to get by and get a grade Problems –May not be fully, tightly specified

Caltech CS184 Winter DeHon Who Am I? Academic History: –LSMSA [state gifted high school, LA] Real Genius summer before senior year –(MIT) 3 [decade] –UCB postdoc ( ) co-ran BRASS group –Caltech start Sept. 1999

Caltech CS184 Winter DeHon What have I done? Started research as a UROP –(Undergrad. Researcher…like SURF) Transit Project –RN1, TC1, Metro, Mlink, MBTA –parallel theory and architecture –SB on fat-tree networks –SM on fault-tolerant, low-latency, large- scale routing networks

Caltech CS184 Winter DeHon RN1 1.2  m CMOS 8-input 8-output Radix-4 Dilation-2 Circuit Switched 50MHz Hot Chips III

Caltech CS184 Winter DeHon TC1 0.8  m CMOS Automatic, Matched Impedance control pads Series terminated 30—100  ISSCC 1993

Caltech CS184 Winter DeHon Reinventing Computing FPGA-coupled processor DPGA (first multicontext FPGA) TSFPGA MATRIX How compare FPGAs and Processors? PhD - Reconfigurable Architectures for General-Purpose Computation

Caltech CS184 Winter DeHon MIT DPGA Prototype w=1, d=1, c=4 p small 9 ns cycle, 1.0  m –LUT –Interconnect –Context read Team: –Jeremy Brown,Derrick Chen –Ian Eslick, Ethan Mirsky –Edward Tau –André DeHon FPD’95 Automatic CAD –multicontext evaluation –FSM partitioning/mapping

Caltech CS184 Winter DeHon MIT MATRIX Testchip Efficient/flexible word size and depth Base unit: –c~4 or 256, d~1 or 128 –w~8 expandable 50MHz, 0.6  m Team: –Ethan Mirsky –Dan Hartman –André DeHon FCCM’96/HotChips’97

Caltech CS184 Winter DeHon BRASS Processor + FPGA Architecture HSRA –fast array, balanced interconnect, retiming –mapping focus DRAM integration (heterogeneous arch.) SCORE –Models/architectural abstractions for RC and beyond

Caltech CS184 Winter DeHon UCB HSRA Testchip Spatial, bit-level –c=1, w=1, d=8, p=2/3 250MHz, 0.4  m DRAM 2Mbit DRAM macro –c~50, d~16K, w~64 Team: –William Tsu, Stelios Perissakis, Randy Huang, Atul Joshi, Michael Chu, Kip Macy, Varghese George, Tony Tung, Omid Rowhani, Norman Walker, John Wawrzynek, André DeHon Automatic retiming –accommodate interconnect pipelining FPGA’99/VLSI Symposium ‘99

Caltech CS184 Winter DeHon

BRASS RISC+HSRA (heterogeneous mix) Integrate: –temporal (processor) –spatial (HSRA) –DRAM instruction data retiming Ideas: –best of both worlds temporal/spatial –exploit 10  DRAM density –SCORE manage spatial pages as virtual resources (like virtual memory) –Compute model  Language  Mapping  Scheduling run-time

Caltech CS184 Winter DeHon Silicon Spice Founded 1997 –by two of my MIT/RC M.Eng. Students –commercialize reconfigurable computing ideas Focus on telecommunication solutions consult for Acquired by Broadcom for $1.2B 2000 CALISTO 240 channel, single-chip VoIP

Caltech CS184 Winter DeHon Caltech IC Group Three Themes: –Compute model beyond ISA? –Interconnect –Molecular Electronics

Caltech CS184 Winter DeHon Universal Nanoscale Architecture Beyond lithographic limits Crossed Wire nanoarrays Implement PLAs, memory, and xbars NSC’02: to appear IEEE TR Nano

Caltech CS184 Winter DeHon Unique Nanoscale Characteristics Can only build very regular structures at nanoscale –Arrays of crossed tubes / wires Will have many defects Switching occurs at tube/wire crossing –Not at substrate…long term 3D opportunity Can store state of switch in wire crossing –Contrast with VLSI where switch >> wire xing Same old architectures won’t make sense here.

Caltech CS184 Winter DeHon What do I want? Develop systematic design Parameterize design space –adapt to costs Understand/capture req. of computing Efficiency metrics –(similar to information theory?)

Caltech CS184 Winter DeHon What do I want? Research vectors: –architecture space –interconnect (beyond one/few PE per die) –SCORE (beyond ISA model) –heterogeneous architectures (beyond monolithic, homogeneous components) –molecular electronics (beyond silicon)

Caltech CS184 Winter DeHon Uniqueness of Class

Caltech CS184 Winter DeHon Not a Traditional Arch. Class Traditional class –focus RISC Processor –history –undergraduate class on uP internals –then graduate class on details This class –much broader in scope –develop design space –see RISC processors in context of alternatives

Caltech CS184 Winter DeHon Authority/History ``Science is the belief in the ignorance of experts.'' -- Richard Feynman Traditional Architecture has been too much about history and authority Should be more about engineering evaluation –physical world is “final authority” Goal: Teach you to think critically and independently about computer design.

Caltech CS184 Winter DeHon On Prerequisites Suggested: –CS20 (compute models, universality) –EE4 (boolean logic, basic logic circuits)

Caltech CS184 Winter DeHon Next Few Lectures Quick run through logic/arithmetic basics –make sure everyone remembers –(some see for first time?) –get us ready to start with observations about the key components of computing devices Trivial/old hat for many –But will be some observations couldn’t make in EE4 May be fast if seeing for first time Background quiz intended to help me tune

Caltech CS184 Winter DeHon Relation to Other Courses CS181 (VLSI) EE4 (Fundamentals of Digital Systems) CS184 (Architecture) CS137 (Electronic Design Automation) CS134 (Compilers and Systems) CS20 (Computational Theory)

Caltech CS184 Winter DeHon Content Overview This quarter: –building blocks and organization –raw components and their consequences Next quarter: –abstractions, models, techniques, systems –will touch on conventional, single-threaded architecture (ISA Processor) –Emphasis likely to be on parallel architectures

Caltech CS184 Winter DeHon Themes (this quarter) Design Space Parameterization Costs Change Structure in Computations

Caltech CS184 Winter DeHon This Quarter Focus on raw computing organization Not worry about –nice abstractions, models Will come back to those next quarter

Caltech CS184 Winter DeHon Change A key feature of the computer industry has been rapid and continual change. We must be prepared to adapt. For our substrate: –capacity (orders of magnitude more) what can put on die, parallelism, need for interconnect and virtualization, homogeneity –speed –relative delay of interconnect and gates

Caltech CS184 Winter DeHon Class Components Lecture Reading [1 required paper/lecture] –No text Weekly assignments Final design/analsysis exercise –(2 weeks)

Caltech CS184 Winter DeHon Lecture Schedule Scheduled MWF 1.5 hrs To allow for lost days –Holidays –Conferences Target use 22 of ideally 30 lectures (standard MW would ideally have 20)

Caltech CS184 Winter DeHon Feedback Will have anonymous feedback sheets for each lecture –Clarity? –Speed? –Vocabulary? –General comments

Caltech CS184 Winter DeHon Fountainhead Quote Howard Roark’s Critique of the Parthenon -- Ayn Rand

Caltech CS184 Winter DeHon Fountainhead Parthenon Quote “Look,” said Roark. “The famous flutings on the famous columns---what are they there for? To hide the joints in wood---when columns were made of wood, only these aren’t, they’re marble. The triglyphs, what are they? Wood. Wooden beams, the way they had to be laid when people began to build wooden shacks. Your Greeks took marble and they made copies of their wooden structures out of it, because others had done it that way. Then your masters of the Renaissance came along and made copies in plaster of copies in marble of copies in wood. Now here we are making copies in steel and concrete of copies in plaster of copies in marble of copies in wood. Why?”

Caltech CS184 Winter DeHon Computer Architecture Parallel Are we making: –copies in submicron CMOS –of copies in early NMOS –of copies in discrete TTL –of vacuum tube computers?

Caltech CS184 Winter DeHon Big Ideas Matter Computes Efficiency of architectures varies widely Computation design is an engineering discipline Costs change  Best solutions (architectures) change Learn to cut through hype –analyze, think, critique, synthesize