EEL5708/Bölöni Lec 8.1 9/19/03 September, 2003 Lotzi Bölöni Fall 2003 EEL 5708 High Performance Computer Architecture Lecture 5 Intel 80x86

EEL5708/Bölöni Lec 8.2 9/19/03 Acknowledgements All the lecture slides were adopted from the slides of David Patterson (1998, 2001) and David E. Culler (2001), Copyright , University of California Berkeley

EEL5708/Bölöni Lec 8.3 9/19/03 Opinions… The x86 isn’t all that complex – it just doesn’t make a lot of sense. Mike Johnson Leader of 80x86 Design at AMD Microprocessor Report (1994) Sour grapes? In the industry “execution” is at least as important as bright ideas Intel, Microsoft: good at execution

EEL5708/Bölöni Lec 8.4 9/19/03 Golden handcuffs 1978 – 8086 assembly language compatible extension of the successful bit microprocessor 1980 – 8087 floating point coprocessor. The architects decided to go with an extended stack architecture (!) 1982 – – new addressing mode (protected), backwards compatibility maintained (real addressing)

EEL5708/Bölöni Lec 8.5 9/19/03 Golden handcuffs (cont’d) 1985 – –Extension to 32 bits. New registers, 32 bit instructions. –New instructions make 386 an almost general purpose register machine. –New addressing mode (segmented addressing) –Backwards compatibility maintained! 1989 – = Pentium, II, III, IV. Only 4 instructions added The basic instruction set seems that it is stabilized.

EEL5708/Bölöni Lec 8.6 9/19/03 Multimedia extensions 1997 – MMX (57 instructions, operating on the existing floating point registers) – SSE (four way single precision 32 bit floating point parallelism on 128 bit registers) 2001 – SSE2 (two way double precision 64 bit parallelism on 128 bit registers). –It allows compilers to use these registers for floating point, instead of the x87 stack architecture

EEL5708/Bölöni Lec 8.7 9/19/03 Register set See figure D.1

EEL5708/Bölöni Lec 8.8 9/19/03 Instruction set Two operand instructions (first operand is also the destination) Allowed combinations: Dest / 1 st operand2 nd operand Register Immediate RegisterMemory Register MemoryImmediate

EEL5708/Bölöni Lec 8.9 9/19/03 Addressing modes Absolute [d] Register indirect [R] Based [Rb+d] Indexed [R+Ri] Based indexed with displacement [R+Ri+d] Based with scaled indexed Based with scaled indexed and displacement [R+(2^I)*Ri+d]

EEL5708/Bölöni Lec /19/03 Segmented addresses Addressing is not absolute: they are relative to segments Original role: to access 20 bit address space with 16 bit registers Now, their main role is memory protection. Segments memory protection modes Four segment registers: CS, DS, SS, ES Every time we address something, we need to make sure which segment we mean (but there are defaults)

EEL5708/Bölöni Lec /19/03 Segmented addressing (cont’d) See figure D.3

EEL5708/Bölöni Lec /19/03 X86 Integer Instructions Data movement instructions: move, push, pop Arithmetic and logic instructions: test, shift, integer, decimal arithmetic Control flow: jumps, branches, calls, returns String instructions: string move, compare

EEL5708/Bölöni Lec /19/03 X86 integer instructions, examples See figure D.4, D.5

EEL5708/Bölöni Lec /19/03 X86 mathematical instructions 80 bit registers, operating like a stack –Loads push numbers on this stack –Operations find operands as top two elements and push result –Stores can pop elements off the stack –There are also some instructions for addressing in the stack Double precision floating point (64 bit) Long integers (64 bit)

EEL5708/Bölöni Lec /19/03 X86 mathematical operations Four classes of instructions Data movement instructions: load, load constant, store Arithmetics: +, -, *, /, square root, absolute value Comparison – sending the result to CPU, to be used in branches Transcendental instructions: sine, cosine, logarithms, exponentiation

EEL5708/Bölöni Lec /19/03 Instruction format Complex, with many different instruction formats Ranges from 1 byte to 17 bytes. Components –Prefixes (repeat, lock, segment override…) –Opcode –Address specifiers –Displacement (8, 16 or 32 bit) –Immediate (8, 16 or 32 bit)

EEL5708/Bölöni Lec /19/03 Comparisons Shortage of general purpose registers Performs about 2-4 times as many memory accesses for floating point than RISC, 1.25 times for integer “Extremely painful addressing scheme” Problem with the floating point scheme (stack is too small). SSE2 fixes this.