The Intel 86 Family of Processors Year Internal Architecture External Bus Size Transistors Principle Features 86 1978 16 29K 16-bit architecture, basic segment protection 88 1979 8 Same as 86, but with 8-bit processor bus. (IBM PC) 286 1982 130K Expands segmentation protection, adds single- instruction task switching (used in IBM PC/AT) Intel 386TM 1985 32 375K Adds paging, 32-bit extensions, on-chip address translation, and greater speed to 286 functions SX 1988 Same as Intel 386 processor, but with a 16-bit data bus

The IntelTM 86 Family of Processors Year Internal Architecture External Bus Size Transistors Principle Features Intel 486TM DX 1989 32 1,200K Adds on-chip cache, floating- point unit, and greater speed to Intel386TM 1991 Intel486TM SX No math, Lower cost The IntelTM 86 Family of Processors DX-2 1992 1.2 Meg Double internal speed PentiumTM P5 - 60,66 64 1993 3.1 Meg Superscaler, Code & Data Cache, 64 bit data bus P54C 1994 3.3 Meg 3.3v, Power Mgt, Multiprocessor support Pro 1995 CPU 5.5 Meg On Chip L1 & L2, Dynamic Execution GTL logic

Pentium™ Processor Architecture Divide Add 64 bit bus Interface Code Cache Prefetch Buffers Integer ALU Register Set Data Cache Branch Prediction Pipelined Floating-Point Unit Multiply U pipe V pipeline 32 bits 64 bits 256 bits

Pentium™ Processor Architecture The Pentium processors have a data bus of 64 bits. This is a 32 bit CPU due to having 32 bits registers. A standard Single Transfer Cycle can read or write up to 64 bits at a time (8 bytes) Burst read and burst write-back cycles are supported by the Pentium processors. Burst Mode cycles are used for Cache operations and transfer 32 bytes in 4 clocks (4 * 8 bytes = 4 * 64 bits). 32 bytes is the size of the Pentium Cache line. For the Pentium, all cache operations are burst cycles.

Pentium™ Processor Architecture Divide Add 64 bit bus Interface Prefetch Buffers Code Cache Integer ALU Register Set Data Cache Branch Prediction Pipelined Floating-Point Unit Multiply U pipeline V pipeline Separate Code and Data caches On chip 8KB code and 8KB write back data cache. Two way set associative. MESI Cache protocol 32 bits 64 bits 256 bits

Pentium™ Processor Architecture Pentium processors include separate Code and Data Caches which can be enabled or disabled by software or hardware. Each cache is 8-Kbytes in size, with a 32-byte line size and is 2-way set associative (4K/way). The Data Cache is configurable to be write-back or write-through on a line-by-line basis and follows MESI protocol. The Instruction Cache is an inherently write-protected cache (read-only)

Pentium™ Processor Architecture Technical Innovations... Branch prediction: Processor makes predictions on next instruction to be executed. Code Cache Branch Prediction 32 bits 64 bits 256 bits Prefetch Buffers Superscalar Architecture more than one execution unit U pipeline V pipeline Pipelined Floating-Point Unit 64 bit bus Interface Integer ALU Integer ALU NOTE: The Instruction Decode Unit is in the Prefetch Buffers on this diagram. Multiply Pipeline sequence Prefetch Decode1 Decode2 Execute Write Back Hardwired Instructions Register Set Add Divide Data Cache

Pentium™ Processor Architecture Instructions are Fetched from the code cache or from the external bus. The decode unit Decodes the prefetched instructions so the Pentium processor can execute the instruction. Branch prediction is implemented with 2 Prefetch Buffers and a Branch Target Buffer so the needed code is almost always prefetched before it is needed for execution. Instructions are executed in 1 of 2 pipelines (“u” & “v” pipes) which share access to a single set of registers. No additional instructions can begin execution until both execution units complete their operations.

Pentium™ Processor Architecture Pentium processors have two instruction pipelines. The u-pipe can Execute all integer and floating point instructions. The v-pipe can Execute simple integer instructions and the floating-point instructions. Pairing instructions in these two pipes enables the Pentium to operate on 2 instructions at the same time (Superscaler execution). The Control ROM unit has direct control over both pipelines. The Control ROM contains microcode which controls the sequence of operations that must be performed.