Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Linear Collider Flavour Identification (LCFI) Overview of the work during the last period Status and plans for the detector R&D:  CPCCDs  Off-sensor electronics  ISIS Future work Konstantin Stefanov (RAL) on behalf of the LCFI collaboration PPRP Open Session, IoP, 8 th September 2004

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Summary of the detector R&D over the last 3 years Main goal – develop Column-Parallel CCD (CPCCD) with CMOS readout First CPCCD (CPC-1) manufactured by e2V with significant input from LCFI CPC-1 successfully tested stand-alone CMOS readout chip (CPR-1) designed at RAL, manufactured by IBM and performing well Hybrid assembly CPC-1/CPR-1 bump bonded by VTT, working fine Everything worked extremely well Next generation devices CPC-2 and CPR-2 near completion Very successful programme overall

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Our first CPCCD (CPC-1) Two phase, pixel size 20 μm  20 μm; 400 (V)  750 (H) pixels; Two charge transport regions; Wire/bump bond connections to readout chip and external electronics. Direct connections and 2-stage source followers 1-stage source followers and direct connections on 20 μm pitch Manufactured by e2V (UK) RAL e2V

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Main parameters of CPC-1 Metal-strapped gates for efficient clock propagation CCD sensitivity  3.1 μV/electron Noise  60 electrons (with filter) Optimised for low voltage operation – works with 1.9 Vpp clock amplitudes  Currently implanted inter-gate barrier  “Stepped nitride” barrier failed in a test wafer – to be resolved for the next device  In future  1 Vpp clock operation could be achieved Clocked to 25 MHz, far beyond the original goal of 1 MHz 15 wafers made available to LCFI, good chips/wafer; CPC-1 wafer with 12 chips, passivated with polyimide RAL e2V

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Bump-bonded CPC-1 to readout chip Bump-bonding done at VTT (solder bumps) Very high quality connections First time e2V CCDs have been bump-bonded Bump-bonded CPC-1/CPR-1 in a test PCB Bump bonds on CPC-1 under microscope Oxford U RAL e2V VTT

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Off-sensor electronics: CPR-1 RAL IBM Wire/bump bond pads 250(W)  132(L)  5-bit FIFO bit flash ADCs Charge Amplifiers Voltage Amplifiers ASIC for CPC-1 readout Designed by the Microelectronics Group at RAL Size : 6 mm  6.5 mm Voltage amplifiers for the 1-stage SF outputs Charge amplifiers for the direct outputs; bit flash ADCs Everything on 20 μm pitch, 0.25 μm CMOS process Fully bump-bondable and partially wire- bondable Scalable and designed to work at 50 MHz Manufactured by IBM

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September CPR-1 response with X-ray signals from CPC-1 Charge channels : 86 mV expected,  70 mV observed – very good agreement; Gain does not change across the array 1-in-3 channels with higher noise due to the wire-bondable pad Voltage channels: Gain in the centre of the array is ½ the gain at the edge Most likely a timing problem Noise ~ 60 electrons

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September CPR-1 and CPC-1 bump bonded RAL VTT IBM 7 assemblies delivered by VTT, 3 tested so far:  All CPC-1 worked perfectly  3 CPR-1 failed because of dicing problems – source is known and will be avoided in the future  3 CPR-1 worked fine, tested with X-rays from 55 Fe source All working CPR-1:  All ADC channels work fine;  All charge amplifiers work  20% of voltage channels with no signal – currently under study CPR-1 is very high speed, extremely sensitive to clock timing Power supply is 2.0 V instead of 2.5 V to improve ADC performance Design of next generation CPR-2 with cluster finding and sparsified readout near completion

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Detector development Detector R&D originally aimed for the “cold” machine, applicable to the “warm” machine as well The cold machine has been selected (20 August 2004) The cold option is much more challenging in terms of signal readout:  Inner layer detector has to be read out at 50 μs intervals during the 1 ms pulse train  Concerns about EMI from RF leakage during readout Two approaches: Fast column parallel CCD with 50 MHz readout:  Currently main detector R&D at LCFI  Established technology  Possible vulnerability to RF pickup ~1000 electrons are read out during the bunch train  Challenge to drive at high speeds In-situ Storage Image Sensor (ISIS), new idea from LCFI (since December 2003):  High immunity to EMI  Several charge samples stored in pixel and read out during the “quiet” period  Could require significant R&D  CPR-1/CPR-2 readout chip applicable to ISIS as well

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Next generation CPCCD : CPC-2 Oxford U RAL e2V Sufficient experience gained with CPC-1 to move to CPC-2 CPC-2 in design phase Large area stitched device (up to 10 cm long) and several smaller chips Even lower clocks amplitudes – stepped nitride barrier definition or low value implants Compatible with CPR-1 and CPR-2 Two charge transport sections Choice of epitaxial layers for different depletion depth Baseline design allows few MHz operation for the largest size CPC-2 Baseline design

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Next generation CPCCD : CPC-2 Oxford U RAL e2V CPC-1 has asymmetric clock distribution and non-optimal drive conditions due to single level metal Novel idea from LCFI for high-speed clock propagation: “busline-free” CCD:  The whole image area serves as a distributed busline  Highest speed potential: 50 MHz achievable with suitable driver Φ1 Φ2 Level 1 metal Polyimide Level 2 metal Φ2 Φ1 To multiple wire bonds To multiple wire bonds 1 mm Apertures for resistance matching

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September RF pickup immunity is an issue for all detectors that convert charge into voltage during the bunch train; Concerns about the RF immunity of the CPCCD triggered the idea of ISIS (In-situ Storage Image Sensor):  Charge collected under a photogate;  Charge is transferred to 20-pixel storage CCD in situ, 20 times during the 1 ms-long train;  Charge is converted to voltage and read out in the 200 ms-long quiet period after the train, RF pickup is avoided;  1 MHz column-parallel readout is sufficient; ISIS Concept ISIS for particle detection

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Additional ISIS advantages:  ~100 times more radiation hard than normal CCDs – less charge transfers  Easier to drive because of the low clock frequency Pure CCD-based ISIS (with no logic) for high-speed imaging already exists; ISIS for particle detection combines CCDs and digital circuitry in one device; Specialised manufacturing process:  Typical CCD technology lacks multi-level metallisation and needs latchup-free CMOS logic  “Standard CMOS” technology cannot implement CCDs Development and design of ISIS is likely to cost a lot more than CPCCD International collaboration is the preferred way forward ISIS Development RAL e2V (DALSA?) (Sarnoff?) Edge logic for row selection and clock gating not shown

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September ISIS Perspective If ISIS is chosen, LCFI likely to collaborate with:  Nijmegen U, NIKHEF (Netherlands) – possible work with DALSA  Yale U, Oregon U (USA) – possible work with Sarnoff LCFI talks and keeps in touch with the world’s experts in the field:  David Burt (e2V) – leading CCD expert  Albert Theuwissen (DALSA) – leading CCD expert, ISIS developer  Jim Janesick (Sarnoff) – expert in both CCD and CMOS imaging e2V agreed to make small ISIS prototype as a part of the CPC-2 wafer batch, at no additional cost:  16  16 array of photogates and buried channel CCD storage cells;  Single level metal, cell pitch 40 μm  160 μm;  No on-chip logic;  Will be evaluated in parallel with CPC-2;

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Driver electronics and radiation damage effects Oxford U Lancaster U Liverpool U RAL Driver electronics: Fast CPCCD represents low impedance load, challenge to drive Driver R&D has started, could require a lot more resources Will expand if CPCCD is chosen Radiation damage effects: LCFI has great expertise in radiation damage effects in CCDs:  Past studies on CCD58 (50 MHz 3-phase CCD)  Currently studies on CPC-1 Help decide between CPCCD and ISIS, provided that EMI is not a problem Choose operating temperature for CPCCD – impact on thin ladder development

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Plans and Summary Plans:  Finish design and evaluate CPC-2, CPR-2 and ISIS-1 till ~Autumn 2005  Meanwhile EMI studies will be carried out (not by LCFI) at SLAC and DESY  If ISIS is the preferred choice – R&D need to be ramped up and coordinated internationally  Will lead to the next 3-year proposal by LCFI LCFI already in very strong position for the cold accelerator LCFI is a strong collaboration between academic research and industry, combining the best of both Our PPARC-funded 3-year programme has been extremely successful, would like to continue the same way