Jing Ye 1,2, Xiaolin Zhang 1,2, Yu Hu 1, and Xiaowei Li 1 1 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese.

Slides:



Advertisements
Similar presentations
An Introduction to the Model Verifier verds Wenhui Zhang September 15 th, 2010.
Advertisements

An Algorithm for Diagnostic Fault Simulation Yu Zhang Vishwani D. Agrawal Auburn University, Auburn, Alabama USA 13/29/2010IEEE LATW 10.
Committee: Vishwani D. Agrawal Adit Singh Victor P. Nelson
10/28/2009VLSI Design & Test Seminar1 Diagnostic Tests and Full- Response Fault Dictionary Vishwani D. Agrawal ECE Dept., Auburn University Auburn, AL.
1 Pattern-Directed Circuit Virtual Partitioning for Test Power Reduction Qiang Xu The Chinese University of Hong Kong Dianwei Hu and Dong Xiang Tsinghua.
1 Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation Dept. of ECE, Auburn University Auburn, AL Hillary Grimes & Vishwani D. Agrawal.
On Diagnosis of Multiple Faults Using Compacted Responses Jing Ye 1,2, Yu Hu 1, and Xiaowei Li 1 1 Key Laboratory of Computer System and Architecture Institute.
Cross-layer Optimized Placement and Routing for FPGA Soft Error Mitigation Keheng Huang 1,2, Yu Hu 1, and Xiaowei Li 1 1 Key Laboratory of Computer System.
Nov. 21, 2006ATS'06 1 Spectral RTL Test Generation for Gate-Level Stuck-at Faults Nitin Yogi and Vishwani D. Agrawal Auburn University, Department of ECE,
Compaction of Diagnostic Test Set for a Full-Response Dictionary Mohammed Ashfaq Shukoor Vishwani D. Agrawal 18th IEEE North Atlantic Test Workshop, 2009.
Partial Implications, etc.
3/30/05Agrawal: Implication Graphs1 Implication Graphs and Logic Testing Vishwani D. Agrawal James J. Danaher Professor Dept. of ECE, Auburn University.
Jan. 29, 2002Gaur, et al.: DELTA'021 A New Transitive Closure Algorithm with Application to Redundancy Identification Vivek Gaur Avant! Corp., Fremont,
Diagnostic Test Generation and Fault Simulation Algorithms for Transition Faults Yu Zhang Vishwani D. Agrawal Auburn University, Auburn, Alabama
Yu Zhang Vishwani D. Agrawal Auburn University, Auburn, Alabama /13/2010 NATW 10 1 A Diagnostic Test Generation System.
A Diagnostic Test Generation System Yu Zhang Vishwani D. Agrawal Auburn University, Auburn, Alabama USA Nov. 3rdITC
Reduced Complexity Test Generation Algorithms for Transition Fault Diagnosis Yu Zhang Vishwani D. Agrawal Auburn University, Auburn, Alabama USA.
May 11, 2006High-Level Spectral ATPG1 High-Level Test Generation for Gate-level Fault Coverage Nitin Yogi and Vishwani D. Agrawal Auburn University Department.
6/11/2015A Fault-Independent etc…1 A Fault-Independent Transitive Closure Algorithm for Redundancy Identification Vishal J. Mehta Kunal K. Dave Vishwani.
Thesis Advisor: Dr. Vishwani D. Agrawal
Dec. 19, 2005ATS05: Agrawal and Doshi1 Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849,
Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA Vishwani D. Agrawal Alok S. Doshi.
Aug 11, 2006Yogi/Agrawal: Spectral Functional ATPG1 Spectral Characterization of Functional Vectors for Gate-level Fault Coverage Tests Nitin Yogi and.
A Two Phase Approach for Minimal Diagnostic Test Set Generation Mohammed Ashfaq Shukoor Vishwani D. Agrawal 14th IEEE European Test Symposium Seville,
Jan. 9, 2007 VLSI Design Conference Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.
Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count- Directed Clustering Aiman El-Maleh and Saqib Khurshid King Fahd University.
A Hybrid Test Compression Technique for Efficient Testing of Systems-on-a-Chip Aiman El-Maleh King Fahd University of Petroleum & Minerals, Dept. of Computer.
Dec. 29, 2005Texas Instruments (India)1 Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849,
Margin Based Sample Weighting for Stable Feature Selection Yue Han, Lei Yu State University of New York at Binghamton.
An Efficient Test Data Reduction Technique Through Dynamic Pattern Mixing Across Multiple Fault Models 2011 VLSI Test Symposium S. Alampally 1, R. T. Venkatesh.
Independence Fault Collapsing
Exclusive Test and its Application to Fault Diagnosis Vishwani D. Agrawal Dong Hyun Baik Yong C. Kim Kewal K. Saluja Kewal K. Saluja.
Jan 6-10th, 2007VLSI Design A Reduced Complexity Algorithm for Minimizing N-Detect Tests Kalyana R. Kantipudi Vishwani D. Agrawal Department of Electrical.
Optimal Tag SNP Selection for Haplotype Reconstruction Jin Jun and Ion Mandoiu Computer Science & Engineering Department University of Connecticut.
March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 1 Nitin Yogi and Dr. Vishwani D. Agrawal Auburn.
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip Aiman El-Maleh 1, Saif al Zahir 2, Esam Khan 1 1 King Fahd University of.
Jan. 6, 2006VLSI Design '061 On the Size and Generation of Minimal N-Detection Tests Kalyana R. Kantipudi Vishwani D. Agrawal Department of Electrical.
Independence Fault Collapsing and Concurrent Test Generation Thesis Advisor: Vishwani D. Agrawal Committee Members: Victor P. Nelson, Charles E. Stroud.
Oct. 5, 2001Agrawal, Kim and Saluja1 Partial Scan Design With Guaranteed Combinational ATPG Vishwani D. Agrawal Agere Systems Processor Architectures and.
Jan. 11, '02Kim, et al., VLSI Design'021 Mutiple Faults: Modeling, Simulation and Test Yong C. Kim University of Wisconsin, Dept. of ECE, Madison, WI 53706,
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits Raja K. K. R. Sandireddy and Vishwani D. Agrawal Dept. Of Electrical and Computer.
黃錫瑜 Shi-Yu Huang National Tsing-Hua University, Taiwan Speeding Up Byzantine Fault Diagnosis Using Symbolic Simulation.
L i a b l eh kC o m p u t i n gL a b o r a t o r y On Effective and Efficient In-Field TSV Repair for Stacked 3D ICs Presenter: Li Jiang Li Jiang †, Fangming.
DYNAMIC TEST SET SELECTION USING IMPLICATION-BASED ON-CHIP DIAGNOSIS Nicholas Imbriglia, Nuno Alves, Elif Alpaslan, Jennifer Dworak Brown University NATW.
1 SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects Qiang Xu and Yubin Zhang Krishnendu Chakrabarty The Chinese.
Master’s Thesis Defense Xiaolu Shi Dept. of ECE, Auburn University
SoC TAM Design to Minimize Test Application Time Huiting Zhang Vishwani D. Agrawal May 12, North Atlantic Test Workshop.
Muralidharan Venkatasubramanian Vishwani D. Agrawal
THE TESTING APPROACH FOR FPGA LOGIC CELLS E. Bareiša, V. Jusas, K. Motiejūnas, R. Šeinauskas Kaunas University of Technology LITHUANIA EWDTW'04.
European Test Symposium, May 28, 2008 Nuno Alves, Jennifer Dworak, and R. Iris Bahar Division of Engineering Brown University Providence, RI Kundan.
1 A Cost-effective Substantial- impact-filter Based Method to Tolerate Voltage Emergencies Songjun Pan 1,2, Yu Hu 1, Xing Hu 1,2, and Xiaowei Li 1 1 Key.
1 Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang National Taiwan.
1 Compacting Test Vector Sets via Strategic Use of Implications Kundan Nepal Electrical Engineering Bucknell University Lewisburg, PA Nuno Alves, Jennifer.
VTS 2012: Zhao-Agrawal1 Net Diagnosis using Stuck-at and Transition Fault Models Lixing Zhao* Vishwani D. Agrawal Department of Electrical and Computer.
A Stable Fixed-outline Floorplanning Method Song Chen and Takeshi Yoshimura Graduate School of IPS, Waseda University March, 2007.
Vishwani D. Agrawal Auburn University, Dept. of Elec. & Comp. Engg. Auburn, AL 36849, U.S.A. Nitin Yogi NVIDIA Corporation, Santa Clara, CA th.
Jing Ye 1,2, Yu Hu 1, and Xiaowei Li 1 1 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences.
Detecting Errors Using Multi-Cycle Invariance Information Nuno Alves, Jennifer Dworak, and R. Iris Bahar Division of Engineering Brown University Providence,
11 Online Computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures Songjun Pan Yu Hu Xiaowei Li {pansongjun, huyu,
A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume Wei-Cheng Lien 1, Kuen-Jong Lee 1 and Tong-Yu.
VLSI Test Symposium, 2011 Nuno Alves, Yiwen Shi, and R. Iris Bahar School of Engineering, Brown University, Providence, RI Jennifer Dworak Department of.
Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects Fei Wang 1,2, Yu Hu 1, Huawei Li 1, Xiaowei Li 1, Jing Ye 1,2 1 Key Laboratory.
Test Generation for Designs with Multiple Clocks Xijiang LinSudhakar M. Reddy Mentor Graphics Corp SW Boeckman Rd. Wilsonville, OR ECE Department.
COE-571 Digital System Testing A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries Authors: P. Bernardi, M. Grosso, M. Rebaudengo,
Fault-Tolerant Resynthesis for Dual-Output LUTs Roy Lee 1, Yu Hu 1, Rupak Majumdar 2, Lei He 1 and Minming Li 3 1 Electrical Engineering Dept., UCLA 2.
Architecture Synthesis for Cost Constrained Fault Tolerant Biochips
Esam Ali Khan M.S. Thesis Defense
A Primal-Dual Solution to Minimal Test Generation Problem
Off-path Leakage Power Aware Routing for SRAM-based FPGAs
Theorems on Redundancy Identification
Presentation transcript:

Jing Ye 1,2, Xiaolin Zhang 1,2, Yu Hu 1, and Xiaowei Li 1 1 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences 2 Graduate University of Chinese Academy of Sciences Substantial Fault Pairs at-A-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method

2 Motivation Fault Diagnosis Quality Efficiency of Diagnosis Method Distinguishability of Used Patterns Distinguish as Many Fault pairs as possible Few More Patterns Than Test Patterns

3 Outline Key Observation Distinguishability of 1-detect compressed Test Patterns Distinguishability of N-detect Test Patterns Related Work Proposed Diagnostic Pattern Generation Method Diagnostic Pattern Generation Method Overview Circuit Transformation and Fault List Creation Diagnostic Pattern Generation Flow Experimental Result Experimental Setting

4 Distinguishability of 1-Detect Compressed Test Patterns Experiment Setting ISCAS’89 benchmark circuits 1-detect compressed test patterns (TetraMax Ver.A ) Fault Pairs Classification two faults in the fault pair are in the same FFR. FP1 type two faults in the fault pair are in different FFRs but with the same observation points. FP2 type two faults in the fault pair are in different FFRs but with at least one different observation points. FP3 type Fanout Free Region (FFR) Key Observation q pq p q pq p q pq p p

5 AVERAGE FP3 typeFP2 typeFP1 type Distinguishability of 1-Detect Compressed Test Patterns Key Observation Percentage of FP i -type fault pairs among all the fault pairs Percentage of indistinguishable FP i -type fault pairs among all the indistinguishable fault pairs FP3 type FP2 type FP1 type

6 AVERAGE Distinguishability of 1-Detect Compressed Test Patterns Key Observation FP1 type fault pairs Two faults in the fault pair are in the same FFR FP2 type fault pairs Two faults in the fault pair are in different FFRs but with the same observation points FP3 type fault pairs Two faults in the fault pair are in different FFRs but with at least one different observation point FP1 > FP2 > FP3 ‘>’ : harder to be distinguished

7 AVERAGE Distinguishability of 1-Detect Compressed Test Patterns Key Observation FP1 type fault pairs Two faults in the fault pair are in the same FFR FP2 type fault pairs Two faults in the fault pair are in different FFRs but with the same observation points FP3 type fault pairs Two faults in the fault pair are in different FFRs but with at least one different observation point FP1 > FP2 > FP3 ‘>’ : harder to be distinguished

8 N-detect test pattern A fault may be detected for multiple times in different ways. Distinguishability of N-Detect Test Patterns Key Observation FP1 type fault pairs

9 Related Work Test elimination process of modifying test patterns [I. Pomeranz, S. M. Reddy TCAD2000] [I. Pomeranz, S. M. Reddy ETS2007] Exclusive test pattern generation [V. D. Agrawal, D. H. Baik, et al. ICVD2003] Pattern generation for fault-tuple modeled faults [N. K. Bhatti, R. D. Blanton ITC2006] Integer linear program formulation [M. A. Shukoor, V. D. Agrawal ETS2009] Pattern distinguishability and N-detect patterns [Z. Wang, M. Marek-Sadowska, et al. ICCD2003] Pattern reordering algorithm for truncated fail data [C. Gang, S. M. Reddy, et al. DAC2006]

10 Diagnostic Pattern Generation Method Overview Proposed Diagnostic Pattern Generation Method

11 Diagnostic Pattern Generation Method Overview Proposed Diagnostic Pattern Generation Method

12 Diagnostic Pattern Generation Method Overview Proposed Diagnostic Pattern Generation Method

13 Diagnostic Pattern Generation Method Overview Proposed Diagnostic Pattern Generation Method Cont.

14 Proposed Diagnostic Pattern Generation Method Circuit Transformation and Fault List Creation Miter circuit Miter circuit is a circuit consisting of two modified duplication D 1 and D 2 of the original circuit. Different connection of D 1 and D 2 is proposed in previous works. S-fault The pattern which can detect a S-fault in the transformed circuit can distinguish its related fault pair in the original circuit. Example Stuck-at v fault at l: l/v. We will work on other fault models in the future. Distinguish the fault pair (a/1,c/1) and the fault pair (b/1,d/1).

15 Proposed Diagnostic Pattern Generation Method Circuit Transformation and Fault List Creation Target fault pair (a/1,c/1) (b/1,d/1) SA1-module ‘out’ = ‘sel’ | ‘in’

16 Proposed Diagnostic Pattern Generation Method Circuit Transformation and Fault List Creation Target fault pair (a/1,c/1) (b/1,d/1) SA1-module ‘out’ = ‘sel’ | ‘in’

17 Proposed Diagnostic Pattern Generation Method Circuit Transformation and Fault List Creation Target fault pair (a/1,c/1) (b/1,d/1) SA1-module ‘out’ = ‘sel’ | ‘in’

18 Proposed Diagnostic Pattern Generation Method Circuit Transformation and Fault List Creation S-fault sel 1 /1 – (a/1,c/1) sel 2 /1 – (b/1,d/1) Target fault pair (a/1,c/1) (b/1,d/1) SA1-module ‘out’ = ‘sel’ | ‘in’

19 Proposed Diagnostic Pattern Generation Method Circuit Transformation and Fault List Creation FAULT-FREE 0 0 S-fault sel 1 /1 – (a/1,c/1) sel 2 /1 – (b/1,d/1) Target fault pair (a/1,c/1) (b/1,d/1) SA1-module ‘out’ = ‘sel’ | ‘in’

20 Proposed Diagnostic Pattern Generation Method Circuit Transformation and Fault List Creation INJECT a/1 INJECT c/1 1 S-fault sel 1 /1 – (a/1,c/1) sel 2 /1 – (b/1,d/1) Target fault pair (a/1,c/1) (b/1,d/1) SA1-module ‘out’ = ‘sel’ | ‘in’

21 Proposed Diagnostic Pattern Generation Method Circuit Transformation and Fault List Creation Fault in original circuit Constrain the value of sel to 0 S-fault sel 1 /1 – (a/1,c/1) sel 2 /1 – (b/1,d/1) Target fault pair (a/1,c/1) (b/1,d/1) SA1-module ‘out’ = ‘sel’ | ‘in’ INJECT h/1 FAULT-FREE 0 0

22 Proposed Diagnostic Pattern Generation Method Diagnostic Pattern Generation Flow FP1 > FP2 > FP3

23 Proposed Diagnostic Pattern Generation Method Diagnostic Pattern Generation Flow

24 Proposed Diagnostic Pattern Generation Method Diagnostic Pattern Generation Flow SAT tool

25 Experimental Setting Experimental Result Benchmark circuit ISCAS’89 ITC’99 Test Pattern TetraMax Ver.A detect compressed test patterns

26 Experimental Data Experimental Result Circuit s5378s9234s13207s15850s35932s38417s38584 Stuck-at faults Test patterns Indistinguished fault pairs FP1 type S-faults Diagnostic patterns Remaining indistinguished S-faults Diagnostic patterns Total diagnostic patterns Fault pairs which cannot be distinguished by any patterns The number of S-faults is mainly determined by the circuit structure The number of S-faults becomes much smaller

27 Comparison with Previous Work Experimental Result [12] I. Pomeranz and S. M. Reddy, "Diagnostic Test Generation Based on Subsets of Faults," Proc. of European Test Symposium (ETS), pp , Comparison with [12] ISCAS’89: almost the same for the small circuits ITC’99: different version of benchmark circuits

28 Comparison with Previous Work Experimental Result [12] I. Pomeranz and S. M. Reddy, "Diagnostic Test Generation Based on Subsets of Faults," Proc. of European Test Symposium (ETS), pp , Comparison with [12] Number of diagnostic patterns in [12] Number of test patterns in [12] About 90% of distinguished fault pairs under diagnostic patterns among indistinguished fault pairs under test patterns in [12] Number of diagnostic patterns in this work Number of test patterns in this work 100% in this work

29 Conclusion Distinguishability of patterns are important ! Distinguishability of 1-detect compressed test patterns FP1 > FP2 > FP3 Miter-circuit and S-fault The pattern which can detect a S-fault in the miter-circuit can distinguish its related fault pair in the original circuit. There is no need to modify the ATPG tool, and the functions of ATPG tool can also be applied.

Thank You for Your Attention ! Any Questions?