Functional Test of Small-Delay Faults using SAT and Craig Interpolation Presenter: Chien-Yen Kuo

ATPG for small delay fault Small delay fault – Assumed to be at the output of a logic gate – Small enough to be detected only with sufficiently long sensitizable path(cf. gross-delay fault) Aim to generate test sequences for these faults in sequential circuit – SATSEQ

SAT-based bounded model checking

Fixed point

Craig interpolation

Model checking flow

MC-instance

Sequence for one fault Consist of 3 sub-sequences

Initial state Two candidates – Synchronized state, if exist, or – Restart state (all-0 state) Synchronized sequence – Sends any state to one and the same state (synchronized state)

Two-pattern delay test To sensitize PO or FF to fault – Pattern 1: Control initial value at fault site – Pattern 2: Control final value and propagate fault Different in at least one PO or FF

Longest sensitizable path

Invalidation and immunity Unexpected fault propagation may invalidate the test – F-invalidation – I-invalidation – P-invalidation – I- and P-invalidation can be ruled out by sufficiently long clock period if no gross-delay fault To avoid F-invalidation (F-immune) – Enforce X (unknown) on all off-path sensitized FF

Fault propagation

Sequence connection

Experimental result

Conclusions SATSEQ, a non-scan ATPG tool for detecting small delay fault in sequential circuit – Less test length compared to scan TAT – Fully deterministic, guarantee to produce shortest possible sub-sequences