IPC In-Circuit Test Fixtures In-circuit test fixtures are commonly called bed-of-nails fixtures. A bed-of- nails fixture is a device with spring contact probes which contact each node on the board under test. The following guidelines should be followed during printed board assembly layout to promote in-circuit testability in bed-of- nails fixtures:

IPC In-Circuit Test Fixtures 1.The diameter of lands of plated- through holes and vias used as test lands are a function of the hole size (see 9.1.1). The diameter of test lands used specifically for probing should be no smaller than 0.9 mm. It is feasible to use 0.6 mm diameter test lands on boards under 7700 mm 2.

IPC In-Circuit Test Fixtures 2.Clearances around test probe sites are dependent on assembly processes. Probe sites should maintain a clearance equal to 80% of an adjacent component height with a minimum of 0.6 mm and a maximum of 5 mm (see Figure 3-1).

IPC In-Circuit Test Fixtures 3.Part height on the probe side of the board must not exceed 5.7mm. Taller parts on this side of the board will require cutouts in the test fixture. Test lands should be located 5 mm away from tall components. This allows for test fixture profiling tolerances during test fixture fabrication.

IPC In-Circuit Test Fixtures 4. No parts or test lands are to be located within 3 mm of the board edges. 5.All probe areas must be solder coated or covered with a conductive non-oxidizing coating. The test lands must be free of solder resist and markings. 6.Probe the test lands or vias, not the termination/castellations of leadless surface mount parts or the leads of leaded parts (see Figure 3-3). Contact pressure can cause an open circuit or make a cold solder joint appear good.

IPC In-Circuit Test Fixtures 7. Avoid requiring probing of both sides of the printed board. Use vias, to bring test points to one side, the bottom side (non- component or solder side of through-hole technology printed board assemblies) of the board. This allows for a reliable and less expensive fixture. 8.Test lands should be on 2.5 mm hole centers, if possible, to allow the use of standard probes and a more reliable fixture.

IPC In-Circuit Test Fixtures 9.Do not rely on edge connector fingers for test lands. Gold plated fingers are easily damaged by test probes. 10.Distribute the test lands evenly over the board area. When the test lands are not evenly distributed or when they are concentrated in one area, the results are board flexing, probing faults, and vacuum sealing problems.

IPC In-Circuit Test Fixtures 11.A test land must be provided for all nodes. A node is defined as an electrical connection between two or more components. A test land requires a signal name (node signal name), the x-y position axis in respect to the printed board datum point, and a location (describing which side of the board the test land is located). This data is required to build a fixture for SMT and mixed technology printed board assemblies.

IPC In-Circuit Test Fixtures 12.Mixed technology printed board assemblies and pin grid component boards provide test access for some nodes at the solder side pins. Pins and vias used at test lands must be identified with node signal name and x-y position in reference to the printed board datum point. Use solder mount lands of parts and connectors as test points to reduce the number of generated test lands.