EE/CS 480 Spring 2008 1February 2008 University of Portland School of Engineering Project Puffins Synchronous Chorded Keypad Input Chip Team RuthAnn Gobble.

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Presentation transcript:

EE/CS 480 Spring February 2008 University of Portland School of Engineering Project Puffins Synchronous Chorded Keypad Input Chip Team RuthAnn Gobble Jordan Way Jonathan Wong Advisor Dr. Aziz Inan Dr. Peter Osterberg Industry Representative Mr. Wes Mickanin

EE/CS 480 Spring February 2008 University of Portland School of Engineering Overview Introduction Scorecard Additional Accomplishments Plans Issues/Concerns Conclusions

EE/CS 480 Spring February 2008 University of Portland School of Engineering Project Puffin will improve security of PIN input devices by exponentially increasing the number of possible PIN combinations. This is done through its use of chorded, synchronous inputs. This will benefit users of ATM’s and other Point of Sale (POS) devices by improving security while increasing pin combinations. Introduction

EE/CS 480 Spring February 2008 University of Portland School of Engineering Scorecard Previous Month’s plans –Complete programming of CPLD and integrate into demo circuit –Purchase buttons to build keypad device to integrate with the demo circuit Shortcomings –Final buttons not purchased

EE/CS 480 Spring February 2008 University of Portland School of Engineering Additional Accomplishments Pin Output received from MOSIS

EE/CS 480 Spring February 2008 University of Portland School of Engineering Plans List your team’s plans for next month –Test CPLD –Build Keypads for FULL test –Replace with MOSIS chip

EE/CS 480 Spring February 2008 University of Portland School of Engineering Milestones NumberDescriptionOriginal 1/14/08 Previous 2/04/08 Present 2/25/08 1Purchase/build demo circuit1/20/082/11/082/30/08 2Program CPLD1/20/082/11/08 3Theory of Operations 0.92/10/082/05/08 4 Initial CPLD debugging on demo-circuit 2/13/08 5 Theory of Operations 0.952/15/082/06/08 6 Theory of Operations 1.02/22/082/07/08 7 Complete CPLD debugging on demo-circuit 2/27/08 2/30/08 8 Integrate MOSIS chip into circuit board and debug 3/16/08 9 Final Report 0.94/11/08 10 Founder’s Day Presentation4/15/08 11 Final Report 0.954/18/08 12 Final Report 1.04/25/08

EE/CS 480 Spring February 2008 University of Portland School of Engineering Concerns/Issues Waiting for MOSIS fabrication to complete so it can be tested along with CPLD Make demo look nice –Visible from back of room Solutions –If MOSIS does not work use CPLD

EE/CS 480 Spring February 2008 University of Portland School of Engineering Conclusion Introduction Scorecard Additional Accomplishments Plans Issues/Concerns Conclusion