Ch.5 Logic Design Standard Cell Design TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology 1

Logic Design Functional Verification Logic Synthesis Scan Path Design RTL Simulation RTL Synthesis Netlist Scan Netlist Timing Analysis Functional Verification 2

5.1 Logic Synthesis 3

Logic Synthesis Problem Map from logic equations to gate-level combinational logic Goals maximize speed minimize power minimize chip/board area Constraints target technology CAD tool CPU time 4

Two-Level vs. Multi-Level PLA control logic constrained layout highly automatic technology independent multi-valued logic input, output, state encoding Very predictable Multi-level Logic all logic general (e.g. standard cell, regular blocks,..) automatic partially technology independent some ideas part of multi-level logic Very hard to predict E.g. Standard Cell Layout 5

6 General Logic Structure Combinational optimization –keep latches/registers at current positions, keep their function –optimize combinational logic in between Sequential optimization –change latch position/function

7 Optimization Criteria for Synthesis The optimization criteria for multi-level logic is to minimize some function of: 1.Area occupied by the logic gates and interconnect (approximated by literals = transistors in technology independent optimization) 2.Critical path delay of the longest path through the logic 3.Degree of testability of the circuit, measured in terms of the percentage of faults covered by a specified set of test vectors for an approximate fault model (e.g., single or multiple stuck-at faults) 4.Power consumed by the logic gates 5.Noise immunity 6.Placeability, Wireability 7.Manufacturability while simultaneously satisfying upper or lower bound constraints placed on these physical quantities

8 Area-Delay Trade-off

5.2 Two Ｌｅｖｅｌ Ｌｏｇｉｃ Ｓ ｙｎｔｈｅｓｉｓ 9

Example (4 Input & 2 Output ） 10

Example (Input Expansion ） Perform logic simplification for the same output. If output is included by the other output, include the Simplification by adding as * or don’t care. 11

Example (Output Reduction ） (4) Input parts is covered by (2). Output (1 1) is reduced to (0 1). F = A’B + C’D +AC G= A D + BC’D +AC 12

5.3 Ｍｕｌｔｉ Ｌｅｖｅｌ Ｌｏｇｉ ｃ Ｓｙｎｔｈｅｓｉｓ 13

Algebraic Division and Boolean Division Algebraic Division F = g K+r where no common cube is included in g and K. F=(a+b)(c+d)+e The other division is Boolean Division. F=(a+b)(a+c)+e 14

Problem of Multi level Logic Synthesis For several logic functions F[i], try to find common divisors such that F[i] = g[i] K+r[i] in a sense of algebraic division. ---->candidate K is restricted to Kernel, which can divide F[i] in algebraic manner. Objective function is the number of literals, which corresponds to size of circuit. F[i]=(ab+a’)(c+d’)+e (#literal =6) 15

Kernel 1. Literals: logic variable or its complement such as A, A’, B, B’ 2. Cube: logic product of literals such as A, AB, AB’ 3. Cube free An expression is cube-free if no cube divides the expression evenly, that is ¬ ∃ C such that F=QC (no remainder), and C is a cube. 4. Kernel The kernel is a logic sum of product terms, which is a cube free. 5. Co-Kernel Co-kernel is a cube, which is a divisor of kernels. 16

Kernel 1. Literals: logic variable or its complement such as A, A’, B, B’ 2. Cube: logic product of literals such as A, AB, AB’ 3. Cube free An expression is cube-free if no cube divides the expression evenly, that is ¬ ∃ C such that F=QC (no remainder), and C is a cube. 4. Kernel The kernel is a logic sum of product terms, which is a cube free. 5. Co-Kernel Co-kernel is a cube, which is a divisor of kernels. 17

Logic Design 2 Kernel Example F=abcd+abce+abef Cofactors={1, ab, abc, abe} Kernels={cd+ce+ef, d+e, c+f} 18

Method to find Kernel 1.Select literal and divide logic function 2.Repeat 1 until cube-free “sum of product” or cube is derived. [Examples] F=abcd+abce+abef 1. select literal a  F1=F/a=bcd+bce+bef 1.1 select literal b  F2=F1/b=cd+ce+ef: cube-free (Kernel) select literal c  F3=F2/c=d+e: cube-free (Kernel) select literal d  F3=F2/d=c (cube) select literal e  F3=F2/e=c+f: cube-free (Kernel) select literal f  F3=F2/f=e (cube) 1.2 select other literal x, but F1/x includes cube b 2. Select other literal x, but F/x includes cube a Cofactors={1, ab, abc, abe} Kernels={cd+ce+ef, d+e, c+f} 19

Example of State Machine 20 ab ｑ1ｑ1 q0 ｄ1ｄ1 ｄ0ｄ １０ 1100 １ １ ０ １

ab ｑ1ｑ1 q0q0 ｄ1ｄ1 ｄ0ｄ ab ∖ q1q １ ｄ 0=bq 1 ’q 0 ’+a’bq 1 ’+a’ ｂ q 0 ’ d1=q 1 q 0 ’+a’q 1 + ｂ q 0 Logic Function I ab ∖ q1q １ 10 １ 21 d1=q 1 q 0 ’+a’q 1 + ｂ q 0

Logic Function II Ｄ 0=bq 1 ’q 0 ’+a’bq 1 ’+a‘ ｂ q 0 ’ Ｄ 1=q 1 q 0 ’+a’q 1 + ｂ q 0 1)Derivation of Kernel Kernel of d0={q 1 ’q 0 ’+a’q 1 ’+a’q 0 ’, q 0 ’+a’, q 1 ’+q 0 ’ } Co-kernel ={b, bq 1 ’, a’b } Kernel of d1={q 1 q 0 ’+a’q 1 +bq 0, q 0 ’+a’} Co-kernel ={1, q 1 } 2) Step 2 Introducing a new variable c=q 0 ’+a’ d0=b(cq 1 ’+a’q 0 ’) =b(cq 1 ’+aq 0 ’) d1=cq 1 +bq 0 22 ｄ 0=bq 1 ’q 0 ’+a’bq 1 ’+a’ ｂ q 0 ’ d1=q 1 q 0 ’+a’q 1 + ｂ q 0

Logic Synthesis I 23

Technology mapping 24

5.4 Scan Path Design 25

Scan Path Design Functional Verification Logic Synthesis Scan Path Design RTL Simulation RTL Synthesis Netlist Scan Netlist Timing Analysis Functional Verification 26

Ｌｏｇｉｃａｌ Ｆａｕｌｔ Ｍｏ ｄｅｌ 1.Stuck-at-0/1 Fault model : Logic value of wire segment is stuck at either logic 0 or logic 1. 2.Single Fault: only one fault happens for each sample. 3.Fault Test: logic circuit is tested by inserting various test input vectors and by observing its output, to check whether any single fault at each wire segment does not occur. 4.ATPG: Automatic Test Pattern Generator is a CAD software to find out necessary input test vectors. 5.Tester: in manufacture factory, tester is implemented so as to check volumes of chips in a short time, automatically. 27

Definition Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. DFT methods for digital circuits: Ad-hoc methods Structured methods: Scan Partial Scan Built-in self-test (BIST) Boundary scan DFT method for mixed-signal circuits: Analog test bus 28

Scan Design Circuit is designed using pre-specified design rules. Test structure (hardware) is added to the verified design: Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO. Use combinational ATPG to obtain tests for all testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test. 29

Logic Design 4 Scan Path Design 1.Change to Test Mode 2.Down load test data to all FF, 3.Change to Run Mode 4.Run in one clock cycle 5.Change to Test Mode 6.Outputs result data from all FF to output of LSI. In test mode, FFs are combined to shift register to set up data of FFs From outside of the chip through a test pin. In similar way, FF values are outputted to the outside of the chip. 30

Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF) D SD MCK Q Q D flip-flop Master latchSlave latch SCK TCK Logic overhead 31

Adding Scan Structure SCANOUT SFF Combinational logic PI PO SCANIN TC or TCK 32

Test Pattern Generation 33

Fault Table 34 ①②③④⑤⑥⑦⑧⑨⑩⑪⑫⑬⑭⑮⑯ 0000 ○ ○ 0001 ○ ○ ○ 0010 ○ ○ 0011 ○○ ○ ○ 0100 ○ ○ ○ ○ 0101 ○○ ○ ○ 0110 ○ ○ ○ ○ 1001 ○ ○ 1010 ○ ○ ○ ○○ 1011○ ○○ ○ ○ ○ 1100 ○ ○ ○ ○ 1101 ○○ ○ ○ 1110 ○ ○ 1111 ○○ ○ ○ ① ｌ１ /0 ⑤ ｌ 3/0, l4/1 ⑨ ｌ 6/0 ⑬ l8/0 ② ｌ１ /1 ⑥ ｌ 3/1, l4/0 ⑩ ｌ 6/1 ⑭ l8/1 ③ ｌ 2/0 ⑦ ｌ 5/0 ⑪ l7/0 ⑮ l9/0 ④ ｌ 2/1 ⑧ ｌ 5/ １⑫ l7/1 ⑯ l9/1 Fault Table indicates the corresponding of test patterns against wire faults ① - ⑯. The fault ⑤ include stuck-at-0 faults for wires l ３ and l4. They are called equivalent fault, which cannot be distinguished by the test at outside. Five test patterns are selected, which can find inside fault by comparing calculated results and measured output against the selected test pattern.