Technical Report High Speed CMOS A/D Converter Circuit for Radio Frequency Signal Kyusun Choi Computer Science and Engineering Department The Pennsylvania State University

Project Goals 1.High speed circuit and layout design 2. Prototype chip fabrication 0.25um and 0.18um CMOS 3. Test and evaluate, explore and improve Core development and silicon test of 6 and 8 bit TIQ based flash ADC

Project Milestones 1.1 st Chip design, 0.25um 12/01/ Chip fabrication 02/05/ Chip testing 04/04/20011 st report 4.2 nd chip design, 0.18um 07/10/20012 nd report, chip 5.Chip fabrication 10/08/ Chip testing 11/09/20013 rd report 7.Project ending 12/31/2001Chip 8.Project presentation 02/15/2002Final report

Project Feature 1.High speed ADC, 1 GSPS 2.RF applications 3.SOC applications, digital CMOS 4.Future-ready, < 0.10um, < 1.0V

TIQ flash ADC gain booster Thermometer code to binary encoder VnVn V3V3 V2V2 V1V1 Vin D1D1 D2D2 D3D3 DkDk gain booster circuit

Other flash ADC Thermometer code to binary encoder –+–+ Vin D1D1 D2D2 D3D3 DkDk V1 V2 V3 –+–+ –+–+ –+–+ Vn V1 V2 V3 Vn R R R R Vref Resistor ladder circuit

TIQ comparator Vr is provided by a voltage references source, External to the voltage comparator Vm is an internal parameter of an inverter, fixed by the transistor sizes Vr _+_+ Vin VrVm Vout VinVoutVmVm DIFFERENTIAL INPUT VOLTAGE COMPARATOR INVERTER

TIQ comparator High speed Less area No resistor ladder and reference voltages No capacitor switching Future ready Scale down Low supply voltage Standard digital logic technology Ideal for SOC

Prototype Test Results 1 st prototype chip (0.25um), six ADCs on chip ADCsPrecisionDelayPower 6bit0.254 bits3.799 ns bit1.006 bits ns bit0.255 bits7.249 ns bit0.507 bits ns bit0.506 bits ns bit1.008 bits ns

Prototype Test Results 2 nd prototype chip (0.18um), ten ADCs on chip ADCsPrecisionDelayPower 6bit1.00FAT6 bit2.65 ns27.0 mW 6bit1.00ROM6 bit4.50 ns21.6 mW 6bit0.50ROM3 bit2.97 ns36.0 mW 6bit0.18ROM3 bit3.35 ns77.4 mW 8bit1.0ROM6 bit15.45 ns64.8 mW 8bit0.50ROM5 bit6.65 ns75.6 mW 9bit1.50ROM5 bit29.20 ns64.8 mW 9bit1.00ROM5 bit36.50 ns111.6 mW

Prototype Test Results ADC: 6 bit 1.00um, ROM, 0.18um prototype chip Input: 100 KHz Saw wave

Prototype Test Results ADC: 6 bit 1.00um, FAT, 0.18um prototype chip Input: 100 KHz Saw wave

Prototype Test Results ADC: 9 bit 1.00um, ROM, 0.25um prototype chip Input: 100 KHz Saw wave

Prototype Test Results ADC: 6 bit 1.00um, FAT, 0.18um prototype chip Input: DC DNL = 0.36 LSB INL = 1.36 LSB

Prototype Test Results ADC: 6 bit 1.00um, FAT, 0.18um prototype chip Input: 80KHz sign wave, f_sample = 10 MHz SNR = dB SNDR = dB SFDR = 9.13 dB ENOB = 3.33 bits

Prototype Test Results ADC: ideal 6 bit Input: 1MHz sign wave, f_sample = 200 MHz SNR = dB SNDR = dB SFDR = dB ENOB = 5.78 bits

Summary High speed ADC for RF application ADC core - 6 and 8 bit design prototype chips (silicon test) 0.25  m and 0.18  m CMOS digital logic technology SOC beyond 0.10um & 1.00V

Innovation/enhancement challenges 1 GSPS with digital CMOS Custom layout generation and modeling CAD tool 8bit and 10bit ADC Low power Low noise Dynamic calibration Offset Gain Temperature Power supply voltage Process parameter variation

Summary High speed ADC for RF application ADC core - 6 and 8 bit design prototype chips (silicon test) 0.25  m and 0.18  m CMOS digital logic technology SOC beyond 0.10um & 1.00V

Chip1 6bit 1.00um, A1:20KH Sine Input A2: Vdd, w/o R on Probs

Chip1 6bit 1.00um, A1: 20KH Sine Input A2: Vdd w/ 4.7K Ohm on Probs

Chip1 6bit 1.00um, A1: 20KH Sine Input A2: Vdd w/ R on Probs

1 st Prototype Chip Test Board

2 nd Prototype Chip Test Board