D0 CFT AFE Module Phase V Test Stand VBA Based Control Code PPD / EED VBA Class Session III May, 18 2004 M. Matulik.

Slides:



Advertisements
Similar presentations
Chapter 3 Basic Input/Output
Advertisements

The CRAY-1 Computer System Richard Russell Communications of the ACM January 1978.
Utilizing the GDB debugger to analyze programs Background and application.
1/1/ / faculty of Electrical Engineering eindhoven university of technology Architectures of Digital Information Systems Part 1: Interrupts and DMA dr.ir.
Chapter 3 Loaders and Linkers
SYSTEM PROGRAMMING & SYSTEM ADMINISTRATION
Programming Languages Marjan Sirjani 2 2. Language Design Issues Design to Run efficiently : early languages Easy to write correctly : new languages.
1/1/ / faculty of Electrical Engineering eindhoven university of technology Introduction Part 3: Input/output and co-processors dr.ir. A.C. Verschueren.
CSS 372 Lecture 1 Course Overview: CSS 372 Web page Syllabus Lab Ettiquette Lab Report Format Review of CSS 371: Simple Computer Architecture Traps Interrupts.
MICE Tracker Front End Progress Tracker Data Readout Basics Progress in Increasing Fraction of Muons Tracker Can Record Determination of Recordable Muons.
1 MICE Tracker Readout Update, Preparation for Cosmic Ray Tests Introduction/Overview AFE-IIt firmware development VLSB firmware development Hardware progress.
Chapter 10 Storage Management Implementation details beyond programmer’s control Storage/CPU time trade-off Binding times to storage.
Computer System Overview
Lecture Notes 1/21/04 Program Design & Intro to Algorithms.
Midterm Tuesday October 23 Covers Chapters 3 through 6 - Buses, Clocks, Timing, Edge Triggering, Level Triggering - Cache Memory Systems - Internal Memory.
CSS 372 Oct 2 nd - Lecture 2 Review of CSS 371: Simple Computer Architecture Chapter 3 – Connecting Computer Components with Buses Typical Bus Structure.
Chapter 8: I/O Streams and Data Files. In this chapter, you will learn about: – I/O file stream objects and functions – Reading and writing character-based.
ARM C Language & Assembler. Using C instead of Java (or Python, or your other favorite language)? C is the de facto standard for embedded systems because.
MICE Tracker Readout Increased Data Readout Rate VLSB Development 16 AFE II t boards 8 Visible Light Photon Counter (VLPC) cassettes 4 cryostats.
Manfred Meyer & IDT & ODT 15 Okt Detectors for Astronomy 2009, ESO Garching, Okt Detector Data Acquisition Hardware Designs.
LAV firmware status Francesco Gonnella Mauro Raggi 23 rd May 2012 TDAQ Working Group Meeting.
©2005 GE Fanuc Automation, Inc. All Rights Reserved PACSystems Training Programmer’s Toolkit.
Chapter 2 Software Tools and Assembly Language Syntax.
Oppenheimer Technologies Rick King Jonathan Creekmore.
Introduction to High-Level Language Programming
Testing. Definition From the dictionary- the means by which the presence, quality, or genuineness of anything is determined; a means of trial. For software.
Chapter 13, Slide 1 Exception Handling Exception handling is a language feature that allows the programmer to handle runtime "exceptional conditions."
Mark Raymond /10/051 Trip-t testing brief status report test setup description - hardware and software some very early results.
สาขาวิชาเทคโนโลยี สารสนเทศ คณะเทคโนโลยีสารสนเทศ และการสื่อสาร.
Data Acquisition Data acquisition (DAQ) basics Connecting Signals Simple DAQ application Computer DAQ Device Terminal Block Cable Sensors.
CHAPTER FOUR COMPUTER SOFTWARE.
Visual Basic for Applications The Datapump Board Jamieson Olsen.
Online Calibration of the D0 Vertex Detector Initialization Procedure and Database Usage Harald Fox D0 Experiment Northwestern University.
Turbine Crane CRANES TURBINE NEA39. Turbine Crane PLANT STATUS! PV Daily Status Report.
January 22, 1999SciFi L1 Trigger Review 1 Analog Hardware Front-end Board (CTT_FE) –Transmit (and split) the VLPC signal to the Multi-chip Modules –Discriminate.
Bob Angstadt Example of a “Front Panel” (Control) Spreadsheet Bob Angstadt May 4, 2004.
UBI >> Contents Chapter 2 Software Development tools Code Composer Essentials v3: Code Debugging Texas Instruments Incorporated University of Beira Interior.
Unit-1 Introduction Prepared by: Prof. Harish I Rathod
A Play Core Timer Interrupts Acted by the Human Microcontroller Ensemble from ENCM511.
ADTs and C++ Classes Classes and Members Constructors The header file and the implementation file Classes and Parameters Operator Overloading.
1 MICE Tracker Readout Update, Preparation for Cosmic Ray Tests Cosmic Ray Tests at RAL AFE-IIt Firmware Development VLSB Firmware Development Summary.
Chapter 1 Introduction. Chapter 1 - Introduction 2 The Goal of Chapter 1 Introduce different forms of language translators Give a high level overview.
1. 2 Preface In the time since the 1986 edition of this book, the world of compiler design has changed significantly 3.
L ECTURE -9 Topics : Compiler Interpreter Loader Linker. Types of Software..
Practical Programming COMP153-08S Week 5 Lecture 1: Screen Design Subroutines and Functions.
FPGA firmware of DC5 FEE. Outline List of issue Data loss issue Command error issue (DCM to FEM) Command lost issue (PC with USB connection to GANDALF)
1Malcolm Ellis - Tracker Meeting - 28th November 2006 Electronics - Station Acceptance  Hardware: u 1 MICE cryostat with 1 VLPC cassette. u VME crate,
Graphical Design Environment for a Reconfigurable Processor IAmE Abstract The Field Programmable Processor Array (FPPA) is a new reconfigurable architecture.
1 MICE Tracker Readout Update Introduction/Overview TriP-t hardware tests AFE IIt firmware development VLSB firmware development Hardware progress Summary.
© 2008, Renesas Technology America, Inc., All Rights Reserved 1 Introduction Purpose  This training course describes Coverage, a utility that is used.
Commands 3/1/ Boot PROM Fundamentals All Sun systems have resident boot PROM firmware Provides basic hardware testing and initialization prior.
1 Asstt. Prof Navjot Kaur Computer Dept PRESENTED BY.
1 Tracker Software Status M. Ellis MICE Collaboration Meeting 27 th June 2005.
XTRP Software Nathan Eddy University of Illinois 2/24/00.
ASIC/FPGA design flow. Design Flow Detailed Design Detailed Design Ideas Design Ideas Device Programming Device Programming Timing Simulation Timing Simulation.
Level-1 Trigger Commissioning Status A.Somov Jefferson Lab Collaboration Meeting, May 10, 2010.
Overview of Compilation Prepared by Manuel E. Bermúdez, Ph.D. Associate Professor University of Florida Programming Language Principles Lecture 2.
COP4020 Programming Languages Introduction Prof. Robert van Engelen (modified by Prof. Em. Chris Lacher)
1 DATE-based DAQ Hideyuki Sakamoto CM22, RAL 19/10/08.
Hello world !!! ASCII representation of hello.c.
EGRE 6311 LHO 04 - Subprograms, Packages, and Libraries EGRE 631 1/26/09.
Status report 2011/7/28 Atsushi Nukariya. Progress Progresses are as follows. 1. FPGA -> Analyze data from FPGA, and some revise point is found. 2. Software.
PC-based L0TP Status Report “on behalf of the Ferrara L0TP Group” Ilaria Neri University of Ferrara and INFN - Italy Ferrara, September 02, 2014.
Code Generation Instruction Selection Higher level instruction -> Low level instruction Register Allocation Which register to assign to hold which items?
"North American" Electronics
Week 3-4 Control flow (review) Function definition Program Structures
Microsoft Office Illustrated
Chap. 8 :: Subroutines and Control Abstraction
Chap. 8 :: Subroutines and Control Abstraction
Exception Handling In Text: Chapter 14.
Presentation transcript:

D0 CFT AFE Module Phase V Test Stand VBA Based Control Code PPD / EED VBA Class Session III May, M. Matulik

EEDEED PPD / EED VBA Session III May 18, 20042

EEDEED PPD / EED VBA Session III May 18, VB_Writew Function VB_Writew(Address As Long, lValue As Long) As Integer Dim i As Integer i = writevmeli(Address, lValue) VB_Writew = i End Function

EEDEED PPD / EED VBA Session III May 18, InitializeSASEQ Static Function InitializeSASEQ(lHDIEnable As Long) As Integer 'Performs the operation of initializing the SASEQ. This results in the SVX chips being placed 'into initialize mode, ready for downloading. In addition, the parameter passed to this procedure 'is used to control the HDI enable bits (controls the output enables on the transceiver(s) connected 'to the SVX control and data busses). ' 'This sequence was copied from the SASEQ initialization list processor worksheet ' 'Required modules: io_617.bas or equivalent ' 'Compiled: M. Matulik Dim iPlace As Integer Dim lAdd As Long Dim lVal As Long InitializeSASEQ = 0 iPlace = VB_clrlatcherri ' clear the latching bit3 status error flg ' Write to SASEQ CROSSWID register lAdd = lSASeqBaseAdd + 6 '0x50D006 lVal = 48 '0x30 iPlace = VB_Writew(lAdd, lVal) ' Write to SASEQ CALVOLT register lAdd = lSASeqBaseAdd + 8 '0x50d008 lVal = 0

EEDEED PPD / EED VBA Session III May 18, InitializeSASEQ lVal = 18 '0x12 iPlace = VB_Writew(lAdd, lVal) ' Write to SASEQ PCID register lAdd = lSASeqBaseAdd + 12 '0x50D00C lVal = 208 '0xD0 iPlace = VB_Writew(lAdd, lVal) ' Write to SASEQ IGNORE register (controls HDI enable) lAdd = lSASeqBaseAdd + 18 '0x50D012 lVal = lHDIEnable '0x03 enable HDI on chain 1 and 2 '0x12 ignore chain 1, enable HDI on chain 2 '0x21 ignore chain 2, enable HDI on chain 1 '0x30 ignore both chains, disable HDIs on both chains iPlace = VB_Writew(lAdd, lVal) ' Write to SASEQ CSR lAdd = lSASeqBaseAdd + 14 '0x50D00E lVal = 166 '0xA6 iPlace = VB_Writew(lAdd, lVal) ' Write to SASEQ TRIGGER register lAdd = lSASeqBaseAdd + 24 '0x50D018 lVal = 0 ' set 132ns mode iPlace = VB_Writew(lAdd, lVal) ' Write to SASEQ TRIGGER register lAdd = lSASeqBaseAdd + 24 '0x50D018 lVal = 128 '0x80 set idle mode iPlace = VB_Writew(lAdd, lVal)

EEDEED PPD / EED VBA Session III May 18, InitializeSASEQ If VB_islatcherri = 0 Then 'No VME errors detected Else InitializeSASEQ = 1 iErrorCode = iSaseqError iTestCode = iSaseqInit iChannelNumber = -1 sErrorValue = -1 iBoardHanded = -1 Call SortErrors End If End Function

EEDEED PPD / EED VBA Session III May 18, 20047

EEDEED PPD / EED VBA Session III May 18, Scope of AFE Test Stand Code  Trivial user entry Entry error checking.  Verify Test Stand Hardware Functionality  Complete Test of AFE Module Verify 1553 Communication Path. Verify the Functionality of the FIFO. Verify Revision Level of Micro Firmware. Download VSVX CPLD parameters.

EEDEED PPD / EED VBA Session III May 18, Scope of AFE Test Stand Code  Complete Test of AFE Module Download SVX parameters. Perform VRef Sweep to determine operating point for each of the 32 SIFT chips on the AFE Module. Use these operating points for subsequent Data Collection.

EEDEED PPD / EED VBA Session III May 18, Scope of AFE Test Stand Code  Complete Test of AFE Module Perform Data Collection Routine. Write test specific values to registers on AFE Module and AFE Test Module. Obtain Digitized Mean and Discriminator Occupancy for all channels. Perform VLPC Bias Voltage and Cryogenic Temperature Control Tests as necessary.

EEDEED PPD / EED VBA Session III May 18, Scope of AFE Test Stand Code  Complete Test of AFE Module Analyze Channel Data for Correct Values of Discriminator Occupancy and Digitized Mean. Three types of AFE Modules can be tested with different expected Mean values.  Generate ACSII files listing results of tests just completed, appending to files of previous test results.

EEDEED PPD / EED VBA Session III May 18, Scope of AFE Test Stand Code  Save raw data of test results to ASCII files for off-line, more extensive data analysis.

EEDEED PPD / EED VBA Session III May 18,

EEDEED PPD / EED VBA Session III May 18,

EEDEED PPD / EED VBA Session III May 18,

EEDEED PPD / EED VBA Session III May 18, Phase V AFE Test Stand VBA code  Collaborative effort, 5+ people writing code.  Highly modular – each code writer responsible for syntax within own module(s).  Pass variables to called functions.  Use of global variables across all modules.

EEDEED PPD / EED VBA Session III May 18, Phase V AFE Test Stand VBA code  Code sections freely stolen from existing/running VBA code, modified to utilize globally defined variables.  Each imported module was required to compile without errors – each code writer was given the most recent copy of the code.  Logic errors corrected during debug.

EEDEED PPD / EED VBA Session III May 18, Phase V AFE Test Stand VBA code  What did we wind up with? A lot of code. A lot of experience. A functioning set of code. A useful base for generating diagnostic programs.

EEDEED PPD / EED VBA Session III May 18, Phase V AFE Test Stand VBA code  What would we change? Don’t rely as much on global variables. Insist on a more common coding style from all of the programmers. Take more time up front to optimize subroutine and function operation.

EEDEED PPD / EED VBA Session III May 18, When you have problems:  Verify logic.  Check passed variables.  Call 2554.