M.Mohajjel

Why? TTM (Time-to-market) Prototyping Reconfigurable and Custom Computing 2Digital System Design

Reprogrammable PLDs Updating a device or correction of errors Reuse device for a different design Ideal for course laboratories 3Digital System Design

Programmable Read-Only Memory (PROM) Single level of programmability Fixed AND-array Programmable OR-array Digital System Design I0I1I2I3I4I0I1I2I3I4 A7 A6 A5 A4 A3 A2 A1 A0 5-to-32 decoder

Programmable Read-Only Memory (PROM) Example Digital System Design5 InputsOutputs I4I3I2I1I0A7A6A5A4A3A2A1A I0I1I2I3I4I0I1I2I3I4 A7 A6 A5 A4 A3 A2 A1 A0 5-to-32 decoder x xxx x x x x x x xx x xx x x x xx x xx x x x x x x x

Field-Programmable Logic Array (PLA) Two levels of configurable logic Programmable AND-array Programmable OR-array Digital System Design6

Field-Programmable Logic Array (PLA) Example Digital System Design7

Programmable Array Logic (PAL) Single level of programmability Programmable AND-array Fixed OR-array Digital System Design8

Programmable Array Logic (PAL) Example Digital System Design9 W = A B C’ + A’ B’ C D’ X = ? Y = ? Z = ?

Simple PLDs (SPLDs) Digital System Design10 Fixed AND array (decoder) Programmable OR array Programmable connections Outputs Inputs Programmable read-only memory (PROM) Programmable AND array Fixed OR array Programmable connections Outputs Inputs Programmable array logic (PAL) device Programmable logic array (PLA) Programmable AND array Programmable OR array Programmable connections Outputs Inputs Programmable connections

Sequential Programmable Devices Digital System Design11

Complex PLDs (CPLDs) Two levels of programmability PLD like blocks Global interconnection matrix Digital System Design12

Field-Programmable Gate Arrays (FPGAs) An array of uncommitted circuit elements, called logic blocks, and interconnect resources Three elements Logic blocks I/O blocks Interconnections Wires Switches Digital System Design13

FPGA Logic Blocks LUT-Based (look-up table) Mux-Based (multiplexer) Digital System Design14

Digital System Design15

Digital System Design16

Digital System Design17

User-Programmable Switch Technologies Fuse Used in PLAs Floating gate transistors Used in CPLDs Digital System Design18

User-Programmable Switch Technologies (cont.) SRAM-controlled Programmable Switches Used in FPGAs Advantages Easily changeable Track latest SRAM technology Disadvantages Volatile High Power dissipation Digital System Design19

User-Programmable Switch Technologies (cont.) SRAM-controlled Programmable Switches Programmable connections Pass-transistor Transmission gate Multiplexer Digital System Design20

User-Programmable Switch Technologies (cont.) Anti-fuse Used in FPGAs Modified CMOS technology Originally open-circuits Digital System Design21

User-Programmable Switch Technologies (cont.) Anti-fuse Advantages Less expensive than SRAM technology Low delay Low power dissipation power Disadvantages One-Time Programmable (OTP) Digital System Design22

User-Programmable Switch Technologies (cont.) Anti-fuse Advantages Less expensive than SRAM technology Low delay Low power dissipation power Disadvantages One-Time Programmable (OTP) Digital System Design23

Evolution of Programmable Logic Devices User-Programmable Switch Technologies (cont.) Digital System Design24

Designing Logic with FPGAs Digital System Design25 Mapping Placement Routing

Designing Logic with FPGAs (cont.) Mapping Example : Using 3-LUTs Digital System Design26

Configuring an FPGA Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory Lose configuration when board power is turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile Memory e.g. PROM or Digital Camera card Digital System Design27 Programming Bit File

Altera CPLDs MAX 7000 Logic Array Blocks (LABs) Programmable Interconnect Array (PIA). Digital System Design28

Altera CPLDs MAX 7000 LAB Two sets of eight macrocells Digital System Design29

Xilinx XC4000 FPGA Configurable Logic Block (CLB) Digital System Design30

Xilinx XC4000 FPGA (cont.) Interconnect structure Digital System Design31

Altera FLEX 8000 FPGA Logic Element (LE) Digital System Design32

Altera FLEX 8000 FPGA (cont.) Carry Chain Digital System Design33

Altera FLEX 8000 FPGA (cont.) Cascade Chain Digital System Design34

Altera FLEX 8000 FPGA (cont.) Logic Array Blocks Local interconnect Digital System Design35

Altera FLEX 8000 FPGA (cont.) FastTrack (global interconnect) Digital System Design36

Altera FLEX FPGA (cont.) Embedded Array Blocks Digital System Design37

Altera FLEX FPGA (cont.) EAB structure Digital System Design38

Xilinx Spartan-6 FPGA CLB Digital System Design39

Xilinx Spartan-6 FPGA SLICE Digital System Design40

Xilinx Spartan-6 FPGA SLICE Digital System Design41

Xilinx Spartan-6 FPGA SLICE Digital System Design42

Xilinx Spartan-6 FPGA LUT6 Digital System Design43

Xilinx Spartan-6 FPGA LUT6 Digital System Design44

Xilinx Spartan-6 FPGA Shift register lookup table (SRL) Digital System Design45

Xilinx Spartan-6 FPGA SLICEM Used as Distributed Memory Digital System Design46

Xilinx Spartan-6 FPGA Block RAM Digital System Design47

Xilinx Spartan-6 FPGA DSP48A1 Slice Digital System Design48

Xilinx Spartan-6 FPGA Interconnect Channels Digital System Design49

Computer Aided Design (CAD) Flow for FPDs Digital System Design50

System on a Chip Add Embedded Micro-Processor Cores in Fabric e.g. RISC PowerPC Ethernet Interface Run Operating System e.g. Linux Combine Micro-Processor & Massively Parallel Logic Dual Design Flows Firmware HDL Software C Digital System Design51