Forward Calorimeter Layer Sum Boards Phase I Upgrade LAr Internal Review J. Rutherfoord 29 May 2015.

Slides:



Advertisements
Similar presentations
Hans Henschel 12-Feb-06FCAL Meeting Cracov 1 FLC-PHY3 Frontend Chip Channels18 Gain values16 (adjustable - 300mv/pC … 5V/pC) 1:1, 1:10 (dynamically selectable.
Advertisements

Muon Tracking FEE R.E. Mischke Los Alamos 10 September, 1999 presentation to the PHENIX Muon Arm Technical Advisory Committee.
Digital Filtering Performance in the ATLAS Level-1 Calorimeter Trigger David Hadley on behalf of the ATLAS Collaboration.
The Pierre-Auger PMT Test Stand Chris Jillings Feb 6, 2002.
SKIROC New generation readout chip for ECAL M. Bouchel, J. Fleury, C. de La Taille, G. Martin-Chassard, L. Raux, IN2P3/LAL Orsay J. Lecoq, G. Bohner S.
A scalable DAQ system using the DRS4 sampling chip H.Friederich 1, G.Davatz 1, U.Hartmann 2, A.Howard 1, H.Meyer 1, D.Murer 1, S.Ritt 2, N.Schlumpf 2 1.
TileCal Electronics A Status Report J. Pilcher 17-Sept-1998.
The LAr ROD Project and Online Activities Arno Straessner and Alain, Daniel, Annie, Manuel, Imma, Eric, Jean-Pierre,... Journée de réflexion du DPNC Centre.
First results from GEM-based Calorimeter prototype for the Linear Collider A.White 4/28/03 (for J.Yu, J.Li, M.Sosebee, S.Habib, V.Kaushik)
Power supply cable Charge injection 3 channels readout (external cables to the scope) 3 channels readout (internal cables) Set up for reading two cards.
EE311: Junior EE Lab Phase Locked Loop J. Carroll 9/3/02.
27 th May 2004Daniel Bowerman1 Dan Bowerman Imperial College 27 th May 2004 Status of the Calice Electromagnetic Calorimeter.
BESIII - ZDD S ervizio E lettronico L aboratori F rascati 1 FEE Block Diagram PM ≈ 3.5 mt (coax cable) X MHz Amplifier 1 of 16 channels ON-DETECTOR.
Status of LAV FEE electronics G. Corradi, C. Paglia, D. Tagnani & M. Raggi, T. Spadaro, P. Valente.
Calorimeter upgrade meeting – CERN – October 5 th 2010 Analog FE ASIC: first prototype Upgrade of the front end electronics of the LHCb calorimeter E.
U niversity of S cience and T echnology of C hina Design for Distributed Scheme of WCDA Readout Electronics CAO Zhe University of Science and Technology.
Preliminary Design of Calorimeter Electronics Shudi Gu June 2002.
16 – 17 Jul 02Andrew Werner TRD Monitor Tube Readout Electronics: Shaping Peter Fisher, Bernard Wadsworth, Andrew Werner MIT 1.
Status of ATF2 Cavity BPM Project Sep 29, 2005 Project Scope: Instrument both couplers ATF2 cavity BPM’s (35) Produce prototype for December cavity test.
PMF: front end board for the ATLAS Luminometer ALFA TWEPP 2008 – 19 th September 2008 Parallel Session B6 – Programmable logic, boards, crates and systems.
FULLY DIFFERENTIAL OPAMP Eduardo Picatoste Calorimeter Electronics Upgrade Meeting.
Readout ASIC for SiPM detector of the CTA new generation camera (ALPS) N.Fouque, R. Hermel, F. Mehrez, Sylvie Rosier-Lees LAPP (Laboratoire d’Annecy le.
Figure 1: ICD Single Channel Block Diagram Schematic PMT High Voltage Supply (see Figure 4 & 4a) LED Pulser PMT Calibration (see Figure 6) ICD Scintillator.
HBD FEM the block diagram preamp – FEM cable Status Stuffs need to be decided….
ATLAS Liquid Argon Calorimeter Monitoring & Data Quality Jessica Levêque Centre de Physique des Particules de Marseille ATLAS Liquid Argon Calorimeter.
Light Calibration System (LCS) Temperature & Voltage Dependence Option 2: Optical system Option 2: LED driver Calibration of the Hadronic Calorimeter Prototype.
B.Satyanarayana, TIFR, Mumbai. Architecture of front-end ASIC INO Collaboration Meeting VECC, Kolkata July 11-13, Amp_out 8:1 Analog Multiplexer.
Two-stage amplifier status test buffer – to be replaced with IRSX i signal recent / final (hopefully) design uses load resistor and voltage gain stage.
HBD FEE test result summary + production schedule 16mv test pulse result –5X attenuator + 20:1 resistor divider at input (to reduce the noise on the test.
SL1Calo Input Signal-Handling Requirements Joint Calorimeter – L1 Trigger Workshop November 2008 Norman Gee.
Update on final LAV front-end M. Raggi, T. Spadaro, P. Valente & G. Corradi, C. Paglia, D. Tagnani.
Towards a final design of LAV front-end M. Raggi, T. Spadaro, P. Valente & G. Corradi, C. Paglia, D. Tagnani.
P. Aspell PACE 3 design meeting 10,11/10/02 Thursday Analog : Morning : DELTA : Delta architecture, project status..... Paul Front-end design
Digital CFEB (an Update) B. Bylsma, EMU at CMS Week, March 16, Ben Bylsma The Ohio State University.
Beam Line BPM Filter Module Nathan Eddy May 31, 2005.
Forward Calorimeter Baseplane and FC1 Layer Sum Board D. Tompkins 30 June 2015.
ERC - Elementary Readout Cell Miguel Ferreira 18 th April 2012
L.Royer– Calice LLR – Feb Laurent Royer, J. Bonnard, S. Manen, P. Gay LPC Clermont-Ferrand R&D pole MicRhAu dedicated to High.
BeamCal Electronics Status FCAL Collaboration Meeting LAL-Orsay, October 5 th, 2007 Gunther Haller, Dietrich Freytag, Martin Breidenbach and Angel Abusleme.
Proposal for LST-based IFR barrel upgrade Roberto Calabrese Ferrara University Workshop on IFR replacement, SLAC, 11/14/2002.
B.Satyanarayana Department of High Energy Physics Tata Institute of Fundamental Research Homi Bhabha Road, Colaba, Mumbai,
Plans and Progress on the FPGA+ADC Card Pack Chris Tully Princeton University Upgrade Workshop, Fermilab October 28, 2009.
Status of the PSD upgrade - Status of the PSD cooling and temperature stabilization system - MAPD gain monitoring system - PSD readout upgrade F.Guber,
Front-End electronics for Future Linear Collider W-Si calorimeter physics prototype B. Bouquet, J. Fleury, C. de La Taille, G. Martin-Chassard LAL Orsay.
1 Timing of the calorimeter monitoring signals 1.Introduction 2.LED trigger signal timing * propagation delay of the broadcast calibration command * calibration.
Mai 31th 2011 Christophe Beigbeder PID meeting1 ETD meeting Test setup : Activities in Bari, Univ of Maryland and at Orsay Test setup : Activities in Bari,
Front-end Electronic for the CALICE ECAL Physic Prototype Christophe de La Taille Julien Fleury Gisèle Martin-Chassard Front-end Electronic for the CALICE.
1 Projectile Spectator Detector: Status and Plans A.Ivashkin (INR, Moscow) PSD performance in Be run. Problems and drawbacks. Future steps.
Digitization at Feed Through Wu, Jinyuan Fermilab Feb
VFE & PCB Status & schedule of production Presented by Julien Fleury Christophe de La Taille, Julien Fleury, Gisèle Martin-Chassard.
PADME Front-End Electronics
Hongda Xu1, Yongda Cai1, Ling Du1, Datao Gong2, and Yun Chiu1
D. Breton, S. Simion February 2012
Jinfan Chang Experimental Physics Center , IHEP Feb 18 , 2011
14-BIT Custom ADC Board Rev. B
Calorimeter Mu2e Development electronics Front-end Review
on behalf of the AGH and UJ PANDA groups
ECAL Front-end development
CTA-LST meeting February 2015
L1Calo Requirements on the DPS
High speed pipelined ADC + Multiplexer for CALICE
ATLAS L1Calo Phase2 Upgrade
Electronics for the E-CAL physics prototype
Christophe de La Taille, Julien Fleury, Gisèle Martin-Chassard
LHCb calorimeter main features
14BIT 125MHz ADC Board for JPARC-K Status Report Mircea Bogdan August 9, 2007 The University of Chicago.
Christophe de La Taille, Julien Fleury, Gisèle Martin-Chassard
STATUS OF SKIROC and ECAL FE PCB
The ATLAS LAr. Calibration board K. Jakobs, U. Schaefer, D. Schroff
Relation (a set of ordered pairs)
Presentation transcript:

Forward Calorimeter Layer Sum Boards Phase I Upgrade LAr Internal Review J. Rutherfoord 29 May 2015

23 September 2014J. Rutherfoord2 FCal LSBs for Phase I Goals of the Phase I upgrade Description of the baseline Present status

One FCal1  -slice 28 May 2015J. Rutherfoord3 Now Proposed Now just 4 trigger towers per  -slice Will be 12 trigger towers per  -slice

FCal front-end is different Trigger summing No summing in depth All LSB inputs are individually weighted by sin(  ) – Of order 10 variation 23 September 2014J. Rutherfoord4

FCal Layer Sum Bds Layer Sum Boards will provide finer segmentation, i.e. less summing. Will maintain legacy summing 23 September 2014J. Rutherfoord5 Layer Sum Board

FCal1 LSB Schematic 23 September 2014J. Rutherfoord6

FCal1 Phase I Layer Sum Board 23 September 2014J. Rutherfoord7

23 September 2014J. Rutherfoord8 Dynamic range Table is everywhere in units of E T In FCal, kinematic limit determined at  s = 14 TeV Choose p T = 512 GeV as upper limit for all FCal trigger towers for now  No saturation! Use shaper linear mixer output upper limit of 3.0 V Set linear mixer gains as low, hi, hi

Resistor values assuming 512 GeV p T and linear mixer 3.00 V 23 September 2014J. Rutherfoord9

Test (dummy) boards Front-End Board (with LSB slots) Calibration board Input from pulse generator to mux which drives 128 lines LTDB with mux from inputs to output to digital scope 23 September 2014J. Rutherfoord10

“Dummy” Front End Board layout 23 September 2014J. Rutherfoord11

FCal1 prototype Phase 1 LSB 23 September 2014J. Rutherfoord12 Input: pin 02 Output: pin 49 Rise: 35 ns Amp: 2.5 Vpp Only one power and one ground pin connected for this test. 100 ns 2.5 V

FCal1 LSB prototype: Normal x-talk 23 September 2014J. Rutherfoord13 Input: 2.5 Vpp Output: 3 mVpp 0.1% x-talk 100 ns 5 mV 2.5 V

FCal1 LSBOnly case of bad x-talk 23 September 2014J. Rutherfoord14 Input: 2.5 Vpp Output: 50 mVpp 2% x-talk 100 ns 50 mV 2.5 V

23 September 2014J. Rutherfoord15 Present status FCal1 LSB pcb stuffed and tested Flaw – One channel in one location has cross- talk exceeding specs. Easy to fix. Possible mix-up on which pair to sum. Three dummy FEB pcbs stuffed – ready to test