chair MPSoC MPSoC Programming Solution “ CoreManager” hardware unit for:  Dependency checking  Task scheduling  Local memory management of PEs  C programmable  No synchronization interrupts  OS scheduling eased Operating System Process Thread t1t2 t3 t4t5 t6 t1t2 t3t4 t6 t5 CP CoreManager TU DresdenSlide 1Heterogeneous MPSoC with Hardware Supported Dynamic Task Scheduling for SDR Processor 0 Processor 1Processor 2 Processor 3

chair TU DresdenSlide 2Heterogeneous MPSoC with Hardware Supported Dynamic Task Scheduling for SDR Heterogeneous MPSoC: ‘Tomahawk’ Vector Fixed Point DSP Scalar Floating Point DSP Core Manager 10 mm Control Processor Scratchpad Memory 5.9 mm² ~280 mW 3.8 mm², ~85 mW 2.5 mm² ~30 mW 3.3 mm², ~27 mW nm UMC; 40 GOPS, MHz LDPC Decoder Filter ASIP Peripherals

chair TU DresdenSlide 3Heterogeneous MPSoC with Hardware Supported Dynamic Task Scheduling for SDR Software Scaling Results 0% or 50% probability of dependence between tasks, 4kB data transfers (in and out)  Hardware task scheduling = power and performance efficient solution for MPSoC programming problem  Scalability depends on:  Task-to-Scheduling time ratio  Inter-Task dependency  Baseband signal processing:  Task time ~10 2 – 10 4 cycles  SW scheduling: ~1000 cycles/task  HW accelerated scheduling: ~60 cycles/task Number of Cores SpeedUp