Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal

Example 1. A simple project implemented just in VHDL FPGA of Spartan IIE family: XC2S300E Pin: T9 48 MHz Divider clkreset Pin: P15 RESET led Pin: C15 LED The example demonstrates all the steps that are required in order to describe, synthesize and implement in FPGA a simple circuit that switches on/off a LED connected to FPGA pin with frequency approximately equal to 1 Hz.

entity led_on_off is Port ( clk : in std_logic; reset : in std_logic; led : out std_logic); end led_on_off; architecture Behavioral of led_on_off is signal internal_clock : std_logic_vector (25 downto 0); begin process(clk,reset) begin if reset = ‘0’ then internal_clock ’0’); elsif clk’event and clk = ‘1’ then internal_clock <= internal_clock+1; end if; end process; led <= internal_clock(internal_clock’left); end Behavioral; Pin: T9 48 MHz Pin: P15 RESET LED VHDL code of the divider

architecture Behavioral of led_on_off is signal internal_clock : std_logic_vector (25 downto 0); begin process(clk,reset) begin if reset = ‘0’ then internal_clock ’0’); elsif clk’event and clk = ‘1’ then internal_clock <= internal_clock+1; end if; end process; led <= internal_clock(internal_clock’left); end Behavioral;  1 sec

Sources in the project. Examples: VHDL files, schematic files, constraints files, library files, etc Processes in current source. Examples: modeling, synthesis, implementation, editing, generation of library symbols, generation of FPGA bitstreams, etc. Editing of different files. Examples: VHDL code, constraints files, etc. Results for active processes. An example: results of synthesis from VHDL

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Sources in the project. Examples: VHDL files, schematic files, constraints files, library files, etc 7

Sources in the project. Examples: VHDL files, schematic files, constraints files, library files, etc 8 9 Next slide

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity led_on_off is Port ( clk : in std_logic; reset : in std_logic; led : out std_logic); end led_on_off; architecture Behavioral of led_on_off is begin end Behavioral; signal internal_clock : std_logic_vector (25 downto 0); process(clk,reset) begin if reset = ‘0’ then internal_clock ’0’); elsif clk’event and clk = ‘1’ then internal_clock <= internal_clock+1; end if; end process; led <= internal_clock(internal_clock’left);

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Left mouse button double click

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MHz HIGH 50% NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 48 MHz HIGH 50 %; 39 40

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drag and drop

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Select 55 Left mouse buttor double click 53

PROGRAM RUN RESET Using Trenz TE-XC2Se prototyping board to check the designed circuit Press

59 Press 61 Press for RESET 60 LED