CPE 626 The SystemC Language Aleksandar Milenkovic Web:

 A. Milenkovic 2 Outline  Writing testbenches  SystemC types  Arrays  Resolved Logic Vector  Clocks

 A. Milenkovic 3 Test Benches  Creating test benches  one process to generate stimulus, the other one to test results  stimulus are generated in the main program, another process test the results  generated and testing are both done in the main program  Typical approach

 A. Milenkovic 4 Example: Counter // Filename : count.h #include "systemc.h" SC_MODULE(count) { sc_in load; sc_in din; sc_in clock;// input ports sc_out dout;// output port int count_val; // internal data st. void count_up(); SC_CTOR(count) { SC_METHOD(count_up); // Method proc. // Sensitive to Rising edge clock sensitive_pos << clock; } }; // Filename : count.cpp #include "count.h" void count::count_up() { if (load) { count_val = din; } else { // Read/Write of local storage count_val = count_val + 1; } // Write to Output port dout = count_val; }

 A. Milenkovic 5 Example: Testbench for Counter #include "systemc.h" SC_MODULE(count_stim) { sc_out load; sc_out din; // input port sc_in clock; // input port sc_in dout; void stimgen(); SC_CTOR(count_stim) { SC_THREAD(stimgen); sensitive_pos (clock); } }; // count_stim.cc #include "count_stim.h" void count_stim::stimgen() { while (true) { load = true; // load 0 din = 0; wait(); // count up, value = 1 load = false; wait(); // count up, value = 2 wait(); // count up, value = 3 wait(); // count up, value = 4 wait(); // count up, value = 5 wait(); // count up, value = 6 wait(); // count up, value = 7 }

 A. Milenkovic 6 Example: Main #include "count.h" #include "count_stim.h" #include "display.h" int sc_main(int argc, char* argv[]) { sc_signal LOAD; sc_signal DIN, DOUT; // clock sc_clock CLOCK("clock", 20); intsim_time = 0; if (argc==2) sim_time = atoi(argv[1]); if (sim_time==0) sim_time = 1000; count u_count ("count"); u_count.load(LOAD); u_count.din(DIN); u_count.dout(DOUT); u_count.clock(CLOCK); count_stim u_count_stim("count_stim"); u_count_stim.load(LOAD); u_count_stim.din(DIN); u_count_stim.dout(DOUT); u_count_stim.clock(CLOCK); display u_display("display"); u_display.dout(DOUT); sc_initialize(); sc_start(sim_time); return(0); }

 A. Milenkovic 7 SystemC Types  SystemC programs may use any C++ type along with any of the built-in ones for modeling systems  long, int, char, short, float, double  SystemC Built-in Types  sc_bit (0, 1), sc_logic (0, 1, X, Z) oTwo- and four-valued single bit

 A. Milenkovic 8 SystemC Types  SystemC Built-in Types  sc_int, sc_unint o1 to 64-bit signed and unsigned integers  sc_bigint, sc_biguint oarbitrary (fixed) width signed and unsigned integers  sc_bv, sc_lv oarbitrary width two- and four-valued vectors  sc_fixed, sc_ufixed osigned and unsigned fixed point numbers  User defined constructs

 A. Milenkovic 9 Ports, Reading&Writing ports  Read&Writing ports  Use read() or write() methods, or  Use assignment operator sc_in // input port of type porttype sc_out // output port of type porttype sc_inout // inout port of type porttype porttype may be any of the types discussed

 A. Milenkovic 10 Arrays sc_in a[32]; // creates ports a[0] to a[31] // of type sc_logic sc_signal i[16]; // creates signals i[0] to // i[15] of type sc_logic

 A. Milenkovic 11 Resolved Logic Vector  More than one driver is driving a signal sc_in_rv x; //input resolved logic vector n bits wide sc_out_rv y;// output resolved logic vector n bits wide sc_inout_rv z; // inout resolved logic vector n bits wide Resolved logic vector port:

 A. Milenkovic 12 Resolved Vector Signals  Used to connect resolved logic vector ports sc_signal_rv sig3; // resolved logic vector signal // n bits wide Resolved logic vector signal:

 A. Milenkovic 13 Clocks  Create clock object named clock1  clock period is 20 time units  duty cycle is 50%  first edge will occur at 2 time units  first value will be true sc_clock clock1("clock1", 20, 0.5, 2, true);