SOLUTION TO module 3.3. Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 112 Example 7.2 Fault A sa0 Step 1 – D-Drive – Set A = 1 D 1 D.

Slides:



Advertisements
Similar presentations
Constraint Satisfaction Problems Russell and Norvig: Chapter
Advertisements

Constraint Satisfaction Problems
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 121 Lecture 12 Advanced Combinational ATPG Algorithms  FAN – Multiple Backtrace (1983)  TOPS – Dominators.
Appendix: Other ATPG algorithms 1. TOPS – Dominators Kirkland and Mercer (1987) n Dominator of g – all paths from g to PO must pass through the dominator.
1 Constraint Satisfaction Problems A Quick Overview (based on AIMA book slides)
1 Constraint Satisfaction Problems. 2 Intro Example: 8-Queens Generate-and-test: 8 8 combinations.
Artificial Intelligence Constraint satisfaction problems Fall 2008 professor: Luigi Ceccaroni.
Review: Constraint Satisfaction Problems How is a CSP defined? How do we solve CSPs?
TOPIC : Backtracking Methodology UNIT 3 : VLSI Testing Module 3.2: Arriving at Input Test Vector.
Constraint Satisfaction Problems
4 Feb 2004CS Constraint Satisfaction1 Constraint Satisfaction Problems Chapter 5 Section 1 – 3.
1 Lecture 11 Major Combinational Automatic Test-Pattern Generation Algorithms n Definitions n D-Algorithm (Roth) D-cubes Bridging faults Logic.
Artificial Intelligence Constraint satisfaction Chapter 5, AIMA.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt1 Lecture 9alt Combinational ATPG (A Shortened version of Original Lectures 9-12) n ATPG problem.
Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 61 Design for Testability Theory and Practice Lecture 6: Combinational ATPG n ATPG problem n Example.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 11alt1 Lecture 11alt Advances in Combinational ATPG Algorithms  Branch and Bound Search  FAN – Multiple.
Constraint Satisfaction Problems
Constraint Satisfaction Problems Russell and Norvig: Chapter 3, Section 3.7 Chapter 4, Pages Slides adapted from: robotics.stanford.edu/~latombe/cs121/2003/home.htm.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 7: February 11, 2008 Static Timing Analysis and Multi-Level Speedup.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 111 Lecture 11 Major Combinational Automatic Test-Pattern Generation Algorithms n Definitions n D-Algorithm.
Chapter 5 Outline Formal definition of CSP CSP Examples
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 101 Lecture 10 Combinational ATPG and Logic Redundancy n Redundancy identification n Redundancy removal.
Spring 08, Apr 8 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Combinational Circuit ATPG Vishwani D. Agrawal.
Testing.
1 Constraint Satisfaction Problems Slides by Prof WELLING.
Unit II Test Generation
VLSI Testing Lecture 7: Combinational ATPG
- 1 -  P. Marwedel, Univ. Dortmund, Informatik 12, 05/06 Universität Dortmund Validation - Simulation and test pattern generation (TPG) -
Chapter 7. Testing of a digital circuit
EE141 Chapter 4 Test Generation.
Hande ÇAKIN IES 503 TERM PROJECT CONSTRAINT SATISFACTION PROBLEMS.
ECE 260B – CSE 241A Testing 1http://vlsicad.ucsd.edu ECE260B – CSE241A Winter 2005 Testing Website:
Universität Dortmund Chapter 6A: Validation Simulation and test pattern generation (TPG) EECE **** Embedded System Design.
12/3/2015 Based on text by S. Mourad "Priciples of Electronic Systems" and M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital,
Zvi Kohavi and Niraj K. Jha 1 Testing of Combinational Circuits.
Maintaining Arc Consistency (MAC) MAC is the same as Back-tracking, but with calls to AC-3 interleaved... function Backtracking-Search(csp) returns.
An Introduction to Artificial Intelligence Lecture 5: Constraint Satisfaction Problems Ramin Halavati In which we see how treating.
1 Constraint Satisfaction Problems Chapter 5 Section 1 – 3 Grand Challenge:
CHAPTER 5 SECTION 1 – 3 4 Feb 2004 CS Constraint Satisfaction 1 Constraint Satisfaction Problems.
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Combinational ATPG.
Technical University Tallinn, ESTONIA Test generation Gate-level methods  Functional testing: universal test sets  Structural test generation  Path.
A New ATPG Algorithm for 21 st Century: The wojoRithm John Sunwoo Electrical & Computer Engineering Auburn University, AL.
EXAMPLE: MAP COLORING. Example: Map coloring Variables — WA, NT, Q, NSW, V, SA, T Domains — D i ={red,green,blue} Constraints — adjacent regions must.
Constraint Satisfaction Problems Rich and Knight: 3.5 Russell and Norvig: Chapter 3, Section 3.7 Chapter 4, Pages Slides adapted from: robotics.stanford.edu/~latombe/cs121/2003/home.htm.
EE141 VLSI Test Principles and Architectures Test Generation 1 1 中科院研究生院课程: VLSI 测试与可测试性设计 第 5 讲 测试生成 (1) 李晓维 中科院计算技术研究所
Division of Polynomials Homework Solutions Feb 19 th Assignment.
Stacks Linear list. One end is called top. Other end is called bottom. Additions to and removals from the top end only.
Page 1EL/CCUT T.-C. Huang Apr TCH CCUT Introduction to IC Test Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech.
Lecture 9 Advanced Combinational ATPG Algorithms
Constraint Satisfaction Problems Lecture # 14, 15 & 16
CS137: Electronic Design Automation
Definitions D-Algorithm (Roth) D-cubes Bridging faults
Definitions D-Algorithm (Roth) D-cubes Bridging faults
VLSI Testing Lecture 7: Combinational ATPG
CPE/EE 428, CPE 528 Testing Combinational Logic (5)
Automatic Test Generation for Combinational Circuits
CPE/EE 428, CPE 528 Testing Combinational Logic (2)
CPE/EE 428, CPE 528 Testing Combinational Logic (4)
Lecture 12 Advanced Combinational ATPG Algorithms
CSP Search Techniques Backtracking Forward checking
A New ATPG Algorithm for 21st Century: The wojoRithm
Fault Models, Fault Simulation and Test Generation
CPE/EE 428, CPE 528 Testing Combinational Logic (3)
VLSI Testing Lecture 7: Combinational ATPG
Automatic Test Pattern Generation
Constraint Satisfaction Problems. A Quick Overview
ELEC Digital Logic Circuits Fall 2015 Logic Testing (Chapter 12)
D-Algorithm (1/4) h d' d i j e' n e k a g b c l f' f m Example 1 D’ G1
GRASP-an efficient SAT solver
CS137: Electronic Design Automation
Presentation transcript:

SOLUTION TO module 3.3

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 112 Example 7.2 Fault A sa0 Step 1 – D-Drive – Set A = 1 D 1 D

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 113 Step 2 -- Example 7.2 D 1 0 D Step 2 – D-Drive – Set f = 0 D

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 114 Step 3 -- Example 7.2 D 1 0 D Step 3 – D-Drive – Set k = 1 D 1 D

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 115 Step 4 -- Example 7.2 D 1 0 D Step 4 – Consistency – Set g = 1 D 1 D 1

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 116 Step 5 -- Example 7.2 D 1 0 D Step 5 – Consistency – f = 0 Already set D 1 D 1

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 117 Step 6 -- Example 7.2 D 1 0 D Step 6 – Consistency – Set c = 0, Set e = 0 D 1 D 1 0 0

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 118 D-Chain Dies -- Example 7.2 D 1 0 X D Step 7 – Consistency – Set B = 0 D-Chain dies D 1 D n Test cube: A, B, C, D, e, f, g, h, k, L

Self assesmenet

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1110 Example 7.3 – Step 2 s sa1 Propagation D-cube for v 1 D 0 sa1 D 1 D

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1111 Example 7.3 – Step 2 s sa1 Forward & Backward Implications 1 D sa1 0 D D

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1112 Example 7.3 – Step 3 s sa1 Propagation D-cube for Z – test found! 1 D sa1 0 D D D

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1113 Example 7.3 – Fault u sa1 Primitive D-cube of Failure 1 D 0 sa1

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1114 Example 7.3 – Step 2 u sa1 Propagation D-cube for v 1 D 0 sa1 D 0

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1115 Example 7.3 – Step 2 u sa1 Forward and backward implications 1 D 0 sa1 D

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1116 Inconsistent d = 0 and m = 1 cannot justify r = 1 (equivalence) – Backtrack – Remove B = 0 assignment

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1117 Example 7.3 – Backtrack Need alternate propagation D-cube for v 1 sa1 D 0

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1118 Example 7.3 – Step 3 u sa1 Propagation D-cube for v 1 sa1 D 0 1 D

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1119 Example 7.3 – Step 4 u sa1 Propagation D-cube for Z D 1 sa1 D 0 1 D 1 1

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1120 Example 7.3 – Step 4 u sa1 Propagation D-cube for Z and implications D 1 sa1 D 0 1 D

PODEM

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1122 Select path s – Y for fault propagation sa1 Example 7.3 Again

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1123 Initial objective: Set r to 1 to sensitize fault 1 sa1 Example Step 2 s sa1

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1124 Example Step 3 s sa1 Backtrace from r 1 sa1

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1125 Example Step 4 s sa1 Set A = 0 in implication stack 1 0 sa1

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1126 Example Step 5 s sa1 Forward implications: d = 0, X = 1 1 sa

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1127 Example Step 6 s sa1 Initial objective: set r to 1 1 sa

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1128 Example Step 7 s sa1 Backtrace from r again 1 sa

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1129 Example Step 8 s sa1 Set B to 1. Implications in stack: A = 0, B = 1 1 sa

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1130 D Example Step 9 s sa1 Forward implications: k = 1, m = 0, r = 1, q = 1, Y = 1, s = D, u = D, v = D, Z = 1 1 sa D D

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1131 Backtrack -- Step 10 s sa1 X-PATH-CHECK shows paths s – Y and s – u – v – Z blocked (D-frontier disappeared) 1 sa

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1132 Step s sa1 Set B = 0 (alternate assignment) 1 sa1 0 0

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1133 Backtrack -- s sa1 1 sa Forward implications: d = 0, X = 1, m = 1, r = 0, s = 1, q = 0, Y = 1, v = 0, Z = 1. Fault not sensitized.

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1134 Step s sa1 Set A = 1 (alternate assignment) 1 sa1 1

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1135 Step s sa1 Backtrace from r again 1 sa1 1

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1136 Step s sa1 Set B = 0. Implications in stack: A = 1, B = 0 1 sa1 1 0

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1137 Backtrack -- s sa1 Forward implications: d = 0, X = 1, m = 1, r = 0. Conflict: fault not sensitized. Backtrack sa

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1138 Step s sa1 Set B = 1 (alternate assignment) 1 sa1 1 1

Feb.. 16, 2001VLSI Test: Bushnell-Agrawal/Lecture 1139 Fault Tested -- Step 18 s sa1 Forward implications: d = 1, m = 1, r = 1, q = 0, s = D, v = D, X = 0, Y = D 1 sa D 0 D D X D