L25 04/16/021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter

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L25 04/16/021 EE Semiconductor Electronics Design Project Spring Lecture 26 Professor Ronald L. Carter

L25 04/16/022 Fig 5.1* Emitter-follower output stage with current-mirror bias. Q3 is gummel conf IR~(V CC -V be )/(R 3 +R 1 ) IQ ~ IR*R1/R2 If Q1 & Q2 FA, then Vi = Vo + Vt ln((IQ+Vo/RL)/IS) If R L large, I o << I Q, so Vi > 0, Vi = Vo + const., until Q1 saturates Vi < 0, the same until Q2 sat at -V CC +V CE2sat RL starts significant conduction at RL3 = (2V CC + V CE2sat )/I Q

L25 04/16/023 Fig 5.2* Transfer char. of the circuit of Fig 5.1 for low (RL2) and high (RL1) values of RL For RL = RL1 > RL3, negl load curr For RL = RL2 < RL3, incl load curr

L25 04/16/024 Fig 5.3* (a) Q1 doesn’t cutoff (b) Q1 does cutoff (1) low input (2) input high enough, or RL low enough to c/o Q1

L25 04/16/025 Fig 5.4* Load lines for RLs (2V CC + V CE2sat )/I Q  RL3 Gives max power (C) R L2 < R L3  power (B) R L1 > R L3  power (A)  max =(1-V CEsat /V CC )/4 ~ 1/4 KVL gives: V CC =V ce1 +(I C1 -I Q )*R L I C1 = (V CC -V ce1 )/R L +I Q

L25 04/16/026 Fig 5.6* Max power Load, mid- point o.c. load Short Circuit load Constant power hyperbolas 2Vcc > BV CEO

L25 04/16/027 Fig 5.7* Low-frequency, small-signal equivalent circuit for the emitter follower Class A: Drive device has an appreciable current(no-cutoff) A v = v o /v i = R L /(R L +1/g m +R s /  o ) R o = 1/g m +R s /  o (… + R L )

L25 04/16/028 Fig 5.10* Simplified ic Class B output stage Q1 (npn) and Q2 (pnp), are a complementary pair   1 =  2 Q1 off if V i < V beOn Q2 off if V i > -V beOn Dead zone: I L = 0 if -V beOn < V i < V beOn I L 

L25 04/16/029 Fig 5.11* Transfer Characteristic of the Class B Stage

L25 04/16/0210 Fig 5.13* Class AB output stage. The gummel diodes reduce crossover distortion.

L25 04/16/0211 Fig 5.20a* Simplified schematic of the 741 output stage Group Project will be similar Optimize current, voltage gain, f T Use Cadence to capture schema- tic, set bias, etc. and gene- rate outputs

L25 04/16/0212 References * Analysis and design of analog integrated circuits, 4th ed., by Gray, Hurst, Lewis and Meyer, Wiley, New York, ©2001.