COMPUTER ORGANIZATIONS CSNB123 Ver.1Systems and Networking1

COMPUTER ORGANIZATIONS CSNB123 Objectives To study the types of semiconductor main memory subsystems  RAM  DRAM  SRAM ROM Error correction Ver.1Systems and Networking2

COMPUTER ORGANIZATIONS CSNB123 Recall: Chapter 4 – Common Memory Parameters Ver.1Systems and Networking3 Memory Type TechnologySize Access Time CacheSemiconductor RAM KB 10 ns Main Memory Semiconductor RAM MB50 ns Magnetic Disk Hard DiskGigabyte10 ms,10 MB/sec Optical DiskCD-ROMGigabyte300 ms, 600 KB/sec Magnetic Tape 100s MBSec-min.,10MB/min

COMPUTER ORGANIZATIONS CSNB123 Semiconductor Main Memory Basic element of semiconductor main memory (smm) – memory cell Cell properties;  2 stable states – 0 and 1  binary  Capable of being written to set the state  Capable of being read to sense the state Ver.1Systems and Networking4

COMPUTER ORGANIZATIONS CSNB123 Memory Cell Operation WriteRead Ver.1Systems and Networking5 Cell Control SelectData in Cell Control SelectSense Functional Terminal - Capable of carrying an electrical signal

COMPUTER ORGANIZATIONS CSNB123 Three Functional Terminals Select terminal – select memory cell for read or write operation Control terminal – indicates read or write  Write – other terminal provides an electrical signal  sets the state of the cell to 1 or 0  Read – that terminal is used for output of the cell’s state Ver.1Systems and Networking6

COMPUTER ORGANIZATIONS CSNB123 Individual words of memory are directly accessed through wired-in addressing logic Ver.1Systems and Networking7

COMPUTER ORGANIZATIONS CSNB123 Semiconductor Memory Types Ver.1Systems and Networking8

COMPUTER ORGANIZATIONS CSNB123 All semiconductor memory is random access DRAM SRAM Ver.1Systems and Networking9

COMPUTER ORGANIZATIONS CSNB123 Random Access Memory (RAM) Characteristic  Read/Write – read data from the memory and to write new data into the memory Use electrical signals  Volatile – must have constant power supply else data lost.  Temporary storage 2 traditional forms of RAM  DRAM  SRAM Ver.1Systems and Networking10

COMPUTER ORGANIZATIONS CSNB123 Dynamic RAM (DRAM) Made with cells that store data as charge on capacitors The presence or absence of charge in a capacitor is interpreted as a binary 1 or 0  Capacitors have tendency of discharging - needs to periodically charge to maintain data storage The term dynamic refers to this tendency of the stored charge to leak away Ver.1Systems and Networking11

COMPUTER ORGANIZATIONS CSNB123 DRAM Structure Figure 5.2 show a typical DRAM structure for an individual cell that stores 1 bit The address line is activated when the bit value from this cell is to be read or written The transistor acts as a switch that is closed (allowing the current to flow) if a voltage is applied to the address line If no current flows, the switch is open means no voltage is present on the address line. Ver.1Systems and Networking12

COMPUTER ORGANIZATIONS CSNB123 DRAM Operation Write A voltage signal is applied to the bit line A high voltage represent 1, a low voltage represent 0 A signal is then applied to the address line allowing a charge to be transferred to the capacitor Read Select address line. The transistor turns on and the charge stored on the capacitor is fed out onto a bit line and to a sense amplifier The sense amplifier compares the capacitor voltage to a reference value and determines if the cell contains a logic 1 or logic 0 The readout from the cell discharges the capacitor which must be restored to complete the operation Ver.1Systems and Networking13

COMPUTER ORGANIZATIONS CSNB123 DRAM (Cont.) Analog device Capacitor stores any charge value within a range  Threshold value – determine whether the charge is interpreted as 0 or1 Ver.1Systems and Networking14

COMPUTER ORGANIZATIONS CSNB123 Static RAM (SRAM) A digital device Use the same logic elements as in the processor The binary values are stored using traditional flip-flop logic gate configuration Data remains as long as power is supplied to it Ver.1Systems and Networking15

COMPUTER ORGANIZATIONS CSNB123 SRAM Structure SRAM structure for an individual cell Four transistors (T1,T2,T3,T4) are cross connected in an arrangement that produces a stable logic state Logic state 1:  C1 is high, C2 is low  T1,T4 are off, T2,T3 are open Logic state 0:  C1 is low, C2 is high  T1,T4 are open, T2,T3 are off The SRAM address line is used to open/close a switch  Controls two transistors (T5,T6)  Apply signal to this line, T5,T6 are switched on, allowing read/write operation Ver.1Systems and Networking16

COMPUTER ORGANIZATIONS CSNB123 SRAM Operation Read The bit value is read from line B Write The desired bit value is applied to line B Its complement is applied at line B Ver.1Systems and Networking17

COMPUTER ORGANIZATIONS CSNB123 DRAM versus SRAM DRAM Simpler to build, smaller More dense Less expensive Needs refresh Larger memory units Use as main memory SRAM Faster Use as cache memory Ver.1Systems and Networking18 Volatile – need power to preserve data

COMPUTER ORGANIZATIONS CSNB123 Read Only Memory (ROM) Permanent storage  Nonvolatile Use in  Microprogramming  Library subroutines  Systems programs (BIOS)  Function tables Ver.1Systems and Networking19

COMPUTER ORGANIZATIONS CSNB123 Types of ROM ROM PROM EPROM EEPROM Flash memory Ver.1Systems and Networking20

COMPUTER ORGANIZATIONS CSNB123 ROM Data is written during manufacture Ver.1Systems and Networking21

COMPUTER ORGANIZATIONS CSNB123 PROM – Programmable ROM Nonvolatile Written once  Electrically – supplier or user  Perform after fabrication  Need special equipment to program Ver.1Systems and Networking22

COMPUTER ORGANIZATIONS CSNB123 EPROM – Erasable PROM Read/write electrically Before a write operation, empty the cells by ultraviolet radiation The erase procedure can be performed repeatedly Expensive than PROM Ver.1Systems and Networking23

COMPUTER ORGANIZATIONS CSNB123 Flash Memory Intermediate between EPROM and EEPROM; cost and functionality Use an electrical erasing tech; much faster than EEPROM Possible to erase just blocks of memory Ver.1Systems and Networking24

COMPUTER ORGANIZATIONS CSNB123 EEPROM – Electrical EPROM Can be written into at any time without erasing prior contents - updates bytes address Write operation is longer than read operation Nonvolatile and flexible in update using ordinary bus control Ver.1Systems and Networking25

COMPUTER ORGANIZATIONS CSNB123 Chip Logic Each chip contains an array of memory cells The array is organized into W words of B bits each. Example : a 16 –Mbit chip could be organized as 1 M 16 words. ( word- is a fixed sized group of bits that are handled as a unit by the instruction set and/or hardware of the processor) Ver.1Systems and Networking26

COMPUTER ORGANIZATIONS CSNB123 Chip Packaging An IC is mounted on a package There are pins used to connect to the outside word Ver.1Systems and Networking27

COMPUTER ORGANIZATIONS CSNB123 Chip Packaging (Cont.) 8 –Mbit chip organization (1M x 8) The organization is treated as a one –word- per chip package. (word -16 bits=2 bytes) There are 32 pins, one of standard chip package Ver.1Systems and Networking28

COMPUTER ORGANIZATIONS CSNB123 Chip Packaging - Pins Support the following signal lines  Address of word being accessed For 1M words, a total of 1M (2 20 ) pins are needed, address A0-A19  The data to be read out-have 8 lines (D0-D7)  The power supply to the chip (Vcc)  A ground pin (Vss)  A chip enable (CE) pin - indicate whether or not the address is valid for this chip  A program voltage (Vpp) - supplied during programming (write op) Ver.1Systems and Networking29

COMPUTER ORGANIZATIONS CSNB123 Interleaved Memory Advance technique used by high-end motherboards/chipsets to improve memory performance Increase bandwidth by allowing simultaneous access to more than one bank of memory Improves performance since CPU/processor can transfer more information to/from memory in the same amount of time, and helps ease the CPU-memory bottleneck Ver.1Systems and Networking30

COMPUTER ORGANIZATIONS CSNB123 Ver.1Systems and Networking31

COMPUTER ORGANIZATIONS CSNB123 Errors A semiconductor memory is subject to errors. Categories;  Hard failures  Soft errors Example : power supply problem Ver.1Systems and Networking32

COMPUTER ORGANIZATIONS CSNB123 Errors – Categories Hard Failures A permanent physical defect so that the memory cells affected cannot reliably store data but become stuck at 0 or 1 Soft Error A random, nondestructive event that alters the contents of one or more memory cells without damaging the memory Ver.1Systems and Networking33

COMPUTER ORGANIZATIONS CSNB123 Process of Detecting and Correcting Errors When data are to be read into memory, a calculation, function f is performed on the data to produce a code Both the code and the data are stored If M –bit word of data is to be stored and the code is of length K bits, then the actual size of the stored word is M + K bits Ver.1Systems and Networking34

COMPUTER ORGANIZATIONS CSNB123 Process of Detecting and Correcting Errors (Cont.) When the previous stored word is read out, the code is used to detect and possibly correct errors A new set of K code bits is generated from the M data bits and compared with the fetched code bits Ver.1Systems and Networking35

COMPUTER ORGANIZATIONS CSNB123 Process of Detecting and Correcting Errors (Cont.) Three results of the comparisons;  No errors-the fetched data bits are sent out  An error is detected-possible to correct, the data bits +error correction bits are fed out into a corrector, which produces a corrected set of M bits to be sent out  An error is detected and connect be corrected, this condition is reported Ver.1Systems and Networking36

COMPUTER ORGANIZATIONS CSNB123 Process of Detecting and Correcting Errors (Cont.) The codes are referred as error-correcting codes A code is characterized by the number of bit errors in a word that it can correct and detect The simplest error-correcting codes is the Hamming code Ver.1Systems and Networking37

COMPUTER ORGANIZATIONS CSNB123 Hamming Code Use to detect and correct one-bit change in an encoded code word Consider the table which has 15 positions. Data is represented (stored) in every position except 1, 2, 4 and 8. These positions are used to store parity (error correction) bits Ver.1Systems and Networking38

COMPUTER ORGANIZATIONS CSNB123 Hamming Code (Cont.) Using the four parity (error correction bits) positions we can represent 15 values (1- 15) Ver.1Systems and Networking39

COMPUTER ORGANIZATIONS CSNB123 Hamming Code (Cont.) Data is represented by the 11 non-parity bit Example: Ver.1Systems and Networking40

COMPUTER ORGANIZATIONS CSNB123 Hamming Code (Cont.) After placing the data in the table, it is in positions 3, 6, 9, 10, 12, 14 and 15 we have a ‘1’ Using the previous conversion table we obtain the binary representation for each of these values Ver.1Systems and Networking41

COMPUTER ORGANIZATIONS CSNB123 Hamming Code (Cont.) We then exclusive OR the resulting values (essentially setting the parity bit to 1 if an odd # of 1’s else setting it to 0 Ver.1Systems and Networking42

COMPUTER ORGANIZATIONS CSNB123 Hamming Code (Cont.) The parity bits are then put in the proper locations in the table providing the following end result: Ver.1Systems and Networking43 This is the encoded code word that would be sent. The receiving side would re-compute the parity bits and compare them to the ones received. If they were the same no error occurred if they were different the location of the flipped bit is determined.

COMPUTER ORGANIZATIONS CSNB123 Hamming Code (Cont.) Assumed now bit at location 14 is flipped, 1 to 0, the calculation for parity is as below: Ver.1Systems and Networking44

COMPUTER ORGANIZATIONS CSNB123 Hamming Code (Cont.) The re-calculated parity information is then compared to the parity information sent/received If they are both the same the result (again using an XOR – even parity) will be all 0’s Ver.1Systems and Networking45

COMPUTER ORGANIZATIONS CSNB123 Hamming Code (Cont.) If a single bit was flipped the resulting number will the position of the errant bit (check back into table). For example: Ver.1Systems and Networking46