George Mason University ECE 545 – Introduction to VHDL Logic Synthesis with Synopsys ECE 545 Lecture 11

2ECE 545 – Introduction to VHDL Basic High-Level Design Flow

3ECE 545 – Introduction to VHDL architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW; VHDL description Circuit netlist Logic Synthesis

4ECE 545 – Introduction to VHDL Basic Synthesis Flow

5ECE 545 – Introduction to VHDL Synthesis using Design Compiler

6ECE 545 – Introduction to VHDL

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8 Scripts

9ECE 545 – Introduction to VHDL Synthesis script (1) designer = "Pawel Chodowiec" company = "George Mason University" search_path = "./opt3/synopsys/TSMCHOME/digital/Front_End/timing_power/tcb013ghp_200a " link_library = "* tcb013ghptc.db" /* Typical case library */ target_library = "tcb013ghptc.db " symbol_library = "tcb013ghp.sdb " /* Directory configuration */ src_directory = ~/exam1/vhdl/ report_directory = ~/exam1/reports/ db_directory = ~/exam1/db/

10ECE 545 – Introduction to VHDL Synthesis script (2) /* Packages can be only read */ read_file -format vhdl -rtl src_directory + "components.vhd" blocks = {regne, upcount, RAM_16Xn_DISTRIBUTED, exam1} foreach (block, blocks) { block_source = src_directory + block + ".vhd" read_file -format vhdl -rtl block_source analyze -format vhdl -lib WORK block_source } current_design block /* All commands now apply to the entity "exam1" */

11ECE 545 – Introduction to VHDL Synthesis script (3) uniquify /* Creates unique instances of multiple refrenced entities */ link check_design /* Checks the current design for consistency */ /*******************************************/ /* apply block attributes and constraints */ /*******************************************/ create_clock -period 10 clk /* Defines that the port "clk" on the entity "clk" is the clock for the design. Period=10ns 50% duty cycle Use -waveform option to define duty cycle other than 50%*/ set_operating_conditions NCCOM /*Normal Case Commercial Operating Conditions*/

12ECE 545 – Introduction to VHDL Synthesis script (4) /***************************************************/ /* Apply these constraints to the top-level entity*/ /***************************************************/ set_max_fanout 100 block set_clock_latency 0.1 find(clock, "clk") set_clock_transition 0.01 find(clock, "clk") set_clock_uncertainty -setup 0.1 find(clock, "clk") set_clock_uncertainty -hold 0.1 find(clock, "clk") set_load 0 all_outputs() set_input_delay 1.0 -clock clk -max all_inputs() set_output_delay -max 1.0 -clock clk all_outputs() set_wire_load_model -library tcb013ghptc -name "TSMC8K_Fsg_Conservative"

13ECE 545 – Introduction to VHDL Wireload model basics (1)

14ECE 545 – Introduction to VHDL Wireload model basics (2)

15ECE 545 – Introduction to VHDL Synthesis script (5) set_dont_touch block compile -map_effort medium change_names -rules vhdl vhdlout_architecture_name = "sort_syn" vhdlout_use_packages = {"IEEE.std_logic_1164"} write -f db -hierarchy -output db_directory + "exam1.db" /*write -f vhdl -hierarchy -output db_directory + "exam1_syn.vhd"*/ report -area > report_directory + "exam1.report_area" report -timing -all > report_directory + "exam1.report_timing"

16ECE 545 – Introduction to VHDL Tips & Hints

17ECE 545 – Introduction to VHDL Tips & Hints (1) Each entity and each package should be placed in a different file. The name of each file should be exactly the same as the name of an entity or package it contains. Arrange entity names in the bottom-up order (the top-most entity at the end of the list) and define this list in your script using the command blocks = { entity1, entity2, …, entityN}

18ECE 545 – Introduction to VHDL Tips & Hints (2) Use only one clock in your entire design. Use an identical name for the clock signal in all your entities and packages (including declarations of components). Use the same clock name in all clock-related commands of your script, such as create_clock, set_clock_transition, etc.

19ECE 545 – Introduction to VHDL Avoid advanced features, such as: multiple clocks, gated clocks, multicycle paths, circular feedback loops containing only combinational logic. Although these features are supported by Synopsys, their correct use requires additional knowledge and experience that are beyond the scope of ECE 545. Tips & Hints (3)

20ECE 545 – Introduction to VHDL Tips & Hints (4) Create a project directory in your main user directory. Create the following subdirectories in the project directory: db, docs, log, reports, scripts, tb, vhdl. Place all your synthesizable source files in the vhdl directory, and your testbench files in the tb directory. Place your scripts in the script directory. Define at least the following directories close to the beginning of your script: src_directory, report_directory, db_directory.

21ECE 545 – Introduction to VHDL Tips & Hints (5) Change your current directory to your log directory before you execute design_analyzer. After executing your script within design_analyzer, analyze the contents of log files generated in the directory log. These files contain the exact description of warnings and errors generated during synthesis. Please do your best to eliminate all errors and majority of warnings generated by the scripts and written to the log files.

22ECE 545 – Introduction to VHDL Results of synthesis

23ECE 545 – Introduction to VHDL Area report after synthesis (1) report_area Information: Updating design information... (UID-85) **************************************** Report : area Design : exam1 Version: V SP1 Date: Tue Nov 15 20:39: **************************************** Library(s) Used: tcb013ghptc (File: /opt3/synopsys/TSMCHOME/digital/Front_End/timing_power/ tcb013ghp_200a/tcb013ghptc.db)

24ECE 545 – Introduction to VHDL Area report after synthesis (2) Number of ports: 75 Number of nets: 346 Number of cells: 107 Number of references: 28 Combinational area: Noncombinational area: Net Interconnect area: undefined (Wire load has zero net area) Total cell area: Total area: undefined

25ECE 545 – Introduction to VHDL Critical Path (1) Critical Path – The Longest Path From Outputs of Registers to Inputs of Registers DQ in clk DQ out t logic t Critical = t FF-P + t logic + t FF-setup

26ECE 545 – Introduction to VHDL Critical Path (2) Min. Clock Period = Length of The Critical Path Max. Clock Frequency = 1 / Min. Clock Period

27ECE 545 – Introduction to VHDL n+m

28ECE 545 – Introduction to VHDL Clock Jitter Rising Edge of The Clock Does Not Occur Precisely Periodically May cause faults in the circuit clk

29ECE 545 – Introduction to VHDL Clock Skew Rising Edge of the Clock Does Not Arrive at Clock Inputs of All Flip-flops at The Same Time DQ in clk DQ out delay DQ in clk DQ out delay

30ECE 545 – Introduction to VHDL H-clock tree used to minimize clock skew

31ECE 545 – Introduction to VHDL Timing report after synthesis (1) **************************************** Report : timing -path full -delay max -max_paths 1 Design : exam1 Version: V SP1 Date : Tue Nov 15 20:39: **************************************** Operating Conditions: NCCOM Library: tcb013ghptc Wire Load Model Mode: segmented

32ECE 545 – Introduction to VHDL Timing report after synthesis (2) Startpoint: in_addr(1) (input port clocked by clk) Endpoint: RegSUM/Q_reg[34] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library exam1 TSMC8K_Fsg_Conservative tcb013ghptc RAM_16Xn_DISTRIBUTED ZeroWireload tcb013ghptc exam1_DW01_cmp2_32_0 ZeroWireload tcb013ghptc exam1_DW01_cmp2_32_1 ZeroWireload tcb013ghptc exam1_DW01_add_35_0 ZeroWireload tcb013ghptc regne_1 ZeroWireload tcb013ghptc regne_2 ZeroWireload tcb013ghptc regne_n35 ZeroWireload tcb013ghptc

33ECE 545 – Introduction to VHDL Timing report after synthesis (3) Point Incr Path clock clk (rise edge) clock network delay (ideal) input external delay f in_addr(1) (in) f U98/Z (CKMUX2D1) f Memory/ADDR[1] (RAM_16Xn_DISTRIBUTED) f Memory/U41/ZN (INVD1) r Memory/U343/Z (OR3D1) r Memory/U338/ZN (INVD2) f Memory/U40/ZN (MOAI22D0) f Memory/U350/Z (OR4D1) f Memory/DATA_OUT[0] (RAM_16Xn_DISTRIBUTED) f

34ECE 545 – Introduction to VHDL Timing report after synthesis (4) add_96xplusxplus/B[0] (exam1_DW01_add_35_0) f add_96xplusxplus/U9/Z (AN2D0) f add_96xplusxplus/U1_1/CO (CMPE32D1) f add_96xplusxplus/U1_2/CO (CMPE32D1) f add_96xplusxplus/U1_3/CO (CMPE32D1) f add_96xplusxplus/U1_4/CO (CMPE32D1) f add_96xplusxplus/U1_5/CO (CMPE32D1) f add_96xplusxplus/U1_6/CO (CMPE32D1) f add_96xplusxplus/U1_7/CO (CMPE32D1) f add_96xplusxplus/U1_8/CO (CMPE32D1) f add_96xplusxplus/U1_9/CO (CMPE32D1) f add_96xplusxplus/U1_10/CO (CMPE32D1) f add_96xplusxplus/U1_11/CO (CMPE32D1) f add_96xplusxplus/U1_12/CO (CMPE32D1) f add_96xplusxplus/U1_13/CO (CMPE32D1) f add_96xplusxplus/U1_14/CO (CMPE32D1) f

35ECE 545 – Introduction to VHDL Timing report after synthesis (5) add_96xplusxplus/U1_15/CO (CMPE32D1) f add_96xplusxplus/U1_16/CO (CMPE32D1) f add_96xplusxplus/U1_17/CO (CMPE32D1) f add_96xplusxplus/U1_18/CO (CMPE32D1) f add_96xplusxplus/U1_19/CO (CMPE32D1) f add_96xplusxplus/U1_20/CO (CMPE32D1) f add_96xplusxplus/U1_21/CO (CMPE32D1) f add_96xplusxplus/U1_22/CO (CMPE32D1) f add_96xplusxplus/U1_23/CO (CMPE32D1) f add_96xplusxplus/U1_24/CO (CMPE32D1) f add_96xplusxplus/U1_25/CO (CMPE32D1) f add_96xplusxplus/U1_26/CO (CMPE32D1) f add_96xplusxplus/U1_27/CO (CMPE32D1) f add_96xplusxplus/U1_28/CO (CMPE32D1) f add_96xplusxplus/U1_29/CO (CMPE32D1) f add_96xplusxplus/U1_30/CO (CMPE32D1) f add_96xplusxplus/U1_31/CO (CMPE32D1) f

36ECE 545 – Introduction to VHDL Timing report after synthesis (6) add_96xplusxplus/U7/Z (AN2D0) f add_96xplusxplus/U5/Z (AN2D0) f add_96xplusxplus/U4/Z (CKXOR2D0) f add_96xplusxplus/SUM[34] (exam1_DW01_add_35_0) f RegSUM/R[34] (regne_n35) f RegSUM/U32/Z (AO21D0) f RegSUM/Q_reg[34]/D (EDFQD1) f data arrival time 5.57

37ECE 545 – Introduction to VHDL Timing report after synthesis (7) clock clk (rise edge) clock network delay (ideal) clock uncertainty RegSUM/Q_reg[34]/CP (EDFQD1) r library setup time data required time data required time 9.88 data arrival time slack (MET) 4.31

38ECE 545 – Introduction to VHDL Timing parameters

39ECE 545 – Introduction to VHDL Timing parameters definition units pipelining delay clock period clock frequency time point  point rising edge  rising edge of clock 1 clock period ns MHz good latency throughput time input  output #output bits/time unit ns Mbits/s bad good

40ECE 545 – Introduction to VHDL register combinational logic one round multiplexer Basic iterative architecture of the encryption/decryption unit round keys enc_dec

41ECE 545 – Introduction to VHDL IN OUT M1 C1 M2 C2 M3 Basic iterative architecture: Timing k · clock_period CLK Latency

42ECE 545 – Introduction to VHDL Increasing throughput using pipelining round 1 round Throughput = target_clock_period block size target clock period, e.g., 20 ns

43ECE 545 – Introduction to VHDL Optimization criteria

44ECE 545 – Introduction to VHDL Degrees of freedom and possible trade-offs speedarea power testability

45ECE 545 – Introduction to VHDL speed area latency throughput Degrees of freedom and possible trade-offs

46ECE 545 – Introduction to VHDL Optimization methods

47ECE 545 – Introduction to VHDL Speed optimization methods (1) better architecture (e.g., CLA vs. ripple carry adder) pipelining parallel processing optimization options of synthesis and implementation tools

48ECE 545 – Introduction to VHDL Speed optimization methods (2) reducing fanout of control signals better state encoding registered outputs from the state machine