Xilinx CPLD Solutions Roadmap

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Presentation transcript:

Xilinx CPLD Solutions Roadmap

CPLD Application Trends High Volume Applications Performance & Density Glue Logic Specialty Functions LSI SSI/MSI 1980s 1990s 2000s Memory Controllers Bus Interfaces UAR/Ts High Speed Clocking Delay Lock Loops Digital Delay Lines Counters State Machines 7400 Series Consumer Set-Top Boxes Cable Modem Bluetooth Home Networking MP3 Interface I2C Networking LVDS Interfaces Line Cards Computers Graphics Cards Printers Industrial The density, performance, and system-level features of Xilinx FPGAs have allowed FPGA applications to evolve from simple glue logic in the 1980s to the heart of programmable systems today.

CPLD Technology Roadmap 0.35 0.25 0.18 0.15 0.13 0.10 0.07 Future technology plans: Metal gates Raised source/drain SiGe substrate SOI (silicon on insulator) 12” wafers lowK dielectric Cu interconnect Feature Size (micron) Xilinx is committed to always having the most advanced process technology available. One of the major advantages of being a fabless semiconductor company is that we can tailor our fab partnerships in order to provide access to the leading edge fab processes. Although we encourage our customers to migrate their designs to lower voltage processes as they become available, we know that many designs will continue to run in production for many years on older processes and Xilinx is committed to supporting those designs. In the next few slides, we will show some examples of Xilinx’s technology leadership. 1999 2000 2001 2002 2003 2004 22

Enhanced Architecture CPLD Product Roadmap Blade Runner I/II/III 1.8/1.5/1.2V Ultra Low Power Lowest Cost XPLA3 3.3V StarFighter I/II 1.8/1.5V High Performance Enhanced Architecture 9500XL/XV 3.3/2.5V Ethernet router PDA Cellular phone Internet appliance Glue logic PAL/GAL integration Lowest Cost MP3 player Laptop docking station Memory controller 9500 5V 1997 2000 2005

CPLD Performance Roadmap tPD (ns) fSYS (MHz) 5.0 4.0 3.5 3.0 2.5 2.0 450 400 350 300 250 200 1.8V technology Flip chip technology Year 1999 2000 2001 2002 2003 2004

CPLD Low Power Roadmap ICC (mA) XPLA Original XPLA Enhanced XPLA3 BladeRunner 50 40 30 20 10 128 macrocell device Eight 16-bit counters @ 50MHz 3.6V, 0o C * estimated for 1.8V device 4mA* 32mA 13mA 50mA

CPLD Product Support Plan 0.5u (5V) XC9500 0.35u (3.3V) XC9500XL 0.25u (2.5V) XC9500XV 0.35u (3.3V) XPLA3 0.18u (1.8V) BladeRunner 0.18u (1.8V) StarFighter 0.15u (1.5V) BladeRunner II 0.15u (1.5V) StarFighter II 1999 2000 2001 2002 2003

WebPOWEREDTM Roadmap WebFITTER Emerald: On-Line Applications Power & Timing Analysis WebPACK Emerald: Integrated CPLD Tool Suite iMPACT ISP Prog ChipViewer IV (point2point timing, editing) Incremental Synthesis XML Reports Exhaustive Mode Fitting (Timing & Area) WebFITTER V3.x: On-Line Applications ChipViewer HDL Editor Power Estimator WebPACK V3.x: SPARTAN Support MARIMBA Install XPLA Bolt-On to ISE Test Vector Utilities WebFITTER V3.1: GUI Redesign Version Control User Options Control New ABEL V7.3 WebPACK V3.1: WebPACK ISE* ABEL V7.3 UNIX Modules XST-ABEL Flow New backPACKs: ECS Schematic Capture VSS StateCAD & HDL Bencher CY2000 CY2001