© 2008, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction Purpose  This course provides an overview of the PWM type Digital-to-Analog (D/A) converter (or simply, D/A) that some H8 series microcontrollers (MCUs) provide. Objectives  Learn about applications for PWM D/As.  Understand the PWM D/A implementation and how this on-chip peripheral function is controlled.  Get tips for applying the on-chip PWM D/A converter included on some H8 series MCUs: the PWM14 (or PWMX) peripheral. Content  19 pages  3 questions Learning Time  25 minutes

© 2008, Renesas Technology America, Inc., All Rights Reserved 2 PWM D/A Applications Radio tuners High-precision voltage-to-frequency converters (VCOs) Digital servo systems And more High-resolution analog-output applications

© 2008, Renesas Technology America, Inc., All Rights Reserved 3 Convert a number to an analog representation while avoiding the pitfalls of implementing analog circuits with digital process technology Offer greater resolution than traditional D/As such as R-2R types Eliminate many of the errors inherent in traditional D/A designs Reduce the constraints on the output filter Renesas Solution: PWM14 D/A Converter  Low impedance digital buffer drives high-impedance analog circuit, eliminating effects of capacitive and resistive loading  Resolution depends only on number of bits in the counter/compare circuit PWM D/A Design Goals D/A Converter

© 2008, Renesas Technology America, Inc., All Rights Reserved 4 PWM Conversion Basics t1t2 t1 = t Volts 2.50 Volts 0V 5V Vout = 1.25 Volts Output level is not affected by frequency if the filter is designed correctly. 0 3 Output A Output B 25% f1f1 f2f2 R C A B Vout = Vcc x Duty Cycle Vout = 2.50 Volts

© 2008, Renesas Technology America, Inc., All Rights Reserved 5 Output Frequency, Filters Nyquist criteria: Must generate output samples at 2x the highest frequency of the waveform being recreated (MINIMUM requirement—faster sample rates are better) Filtering the output: If you output samples at twice the frequency, you may need a filter with a very sharp roll-off to decrease ripple to an acceptable level. Sampling at higher rates allows the use of simpler, less-expensive filters.

© 2008, Renesas Technology America, Inc., All Rights Reserved 7 H8 PWM D/A Converter DACR: PWM D/A Control Register (6 bits) DADRA: PWM D/A Data Register A (15 bits) DADRB: PWM D/A Data Register B (15 bits) DACNT: PWM D/A Counter (14 bits) Module Data Bus PWX0 PWX1 Bus Interface Internal Clock Ø Basic Cycle Compare-match A Basic Cycle Compare-match B Fine-adjustment Pulse Addition B Fine-adjustment Pulse Addition A Basic Cycle Overflow Internal Data Bus Comparator A Comparator B 14-bit Up Counter (DACNT) Data Register (DADRA) Control Register (DACR) Control Logic Clock Selection Module Stop Ø/2 Clock Data Register (DADRB) All-digital design

© 2008, Renesas Technology America, Inc., All Rights Reserved 8 Registers in Detail  IIEC: Controls the multiplexing of the access to the SCI and the IIC / PWMX registers  REGS: Controls access to various registers within the PWMX peripheral. Design issue: You must use a software driver that will maintain the values of these pointer bits when a context switch occurs within the application. In some H8 MCUs, various addresses are shared by different registers within a module.

© 2008, Renesas Technology America, Inc., All Rights Reserved 9 Counter Register Design tips: - Writing to this register will affect the conversion cycle on both channels (PWMX0 and PWMX1) of the PWM14 converter. - When reading this register, shift down by 2 to isolate the counter bits (i.e., count_value = DACNT >> 2). Design constraint: DACNT register must be written and read with a 16-bit access. (An 8-bit access will yield incorrect results.) DACNT

© 2008, Renesas Technology America, Inc., All Rights Reserved 10 DA Data Registers Design constraints:- Although the register could be read with either an 8-bit or 16-bit access; however, you must write it using a 16-bit access to get correct results. - Only certain values will actually cause a pulse to be output on the output pin, based on the CFS bit. DADR

© 2008, Renesas Technology America, Inc., All Rights Reserved 11 PWM14 Control Register Clock Select (0 = system clock = t cyc ; 1 = system clock/2 = t cyc x 2) Output select (0 = DIRECT = sum the low part of the waveform; 1 = INVERTED = sum the high parts of the waveform PWM Enable (0=disabled; 1 = enabled) Controls the output of the individual channels (0=disabled 1= enabled. [These are the ONLY channel-unique bits in this register.] ) Design tip: Do not use the TEST bit in a normal application; doing so will cause improper converter operation. DACR

© 2008, Renesas Technology America, Inc., All Rights Reserved 13 Controlling the PWM output When CKS = 0, T = t PROCESSOR CLOCK When CKS = 1, T = (t PROCESSOR CLOCK ) x 2 Conversion time = T x (for 14-bit resolution) Basic Cycle: If CFS = 0, t f = T x 64 If CFS = 1, t f = T x 256 Output:If OS = 0, DACNT represents total t L time If OS = 1, DACNT represents total t H time tLtL tHtH CKS = 0 CKS = 1 If CKS=0, the T = 1/10MHz conversion = T x = µs With this CKS setting, if CFS = 0, Base cycle = T x 64 = 1/10MHz x 64 = 6.4µs if CFS = 1, Base cycle = T x 256 = 1/10MHz x 256 = 25.6µs If CKS=1, the T = (1/10MHz) x 2 conversion = T x 2 x = µs With this CKS setting: if CFS = 0, Base cycle = T x 64 = 1/10MHz x 2 x 64 = 12.8µs if CFS = 1, Base cycle = T x 256 = 1/10MHz x 2 x 256 = 51.2µs

© 2008, Renesas Technology America, Inc., All Rights Reserved 14 Filters Revisited For a 10MHz CPU clock and a 14-bit PWM D/A conversion: Conversion time = µs Basic cycle = 6.4µs Therefore, the basic cycle is a full 8 octaves below the conversion frequency. Remnants of the basic cycle will be about 48dB below the conversion frequency. Assuming that we are trying to recreate the conversion frequency, remnants of the basic cycle are still 42dB below the frequency we are trying to recover. From PWM D/A To analog circuit R C

© 2008, Renesas Technology America, Inc., All Rights Reserved 15 Maximum Output Frequency According to the Nyquist criteria, the theoretical maximum frequency that the PWM D/A can generate = 1/2 x Conversion time.  With a 10MHz clock and a full 14-bit conversion: – Conversion time = µs – Highest output frequency = Hz  With a 10MHz clock and a 10-bit conversion: – Conversion time = 102.4µs – Highest output frequency = Hz

© 2008, Renesas Technology America, Inc., All Rights Reserved 16 High-Accuracy Digital Servo MCU Outside the Feedback Loop MCU Filter Voice-Coil Motor PWM D/A Out Driver Position Feedback Signal to Track Analog Control Circuit ∑ Calibration

© 2008, Renesas Technology America, Inc., All Rights Reserved 17 High-Accuracy Digital Servo Microcontroller Filter Voice-Coil Motor PWM D/A Out Driver Position Feedback Signal to Track MCU Inside the Feedback Loop

© 2008, Renesas Technology America, Inc., All Rights Reserved 19 Summary PWM D/A basics H8 PWMX design Registers Design tips Applications