2/10/07DSD,USIT,GGSIPU1 BCD adder KB3B2B1B0CD3D2D1D0 0000000000 0000100001 0001000010 0001100011 0010000100 0010100101 0011000110 0011100111 0100001000.

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2/10/07DSD,USIT,GGSIPU1 BCD adder KB3B2B1B0CD3D2D1D

2/10/07DSD,USIT,GGSIPU2 4-Bit adder

2/10/07DSD,USIT,GGSIPU3 VHDL code for BCD adder entity BCDadder is Port ( bcd1 : in std_logic_vector(3 downto 0); bcd2 : in std_logic_vector(3 downto 0); bcdcarryin : in std_logic; bcdsum : out std_logic_vector(3 downto 0); bcdcarryout : out std_logic); end BCDadder;

2/10/07DSD,USIT,GGSIPU4 architecture Behavioral of BCDadder is component adder4bit is Port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); carryin : in std_logic; sum : out std_logic_vector(3 downto 0); carryout : out std_logic); end component adder4bit; signal s,x: std_logic_vector(3 Downto 0); signal c,K : std_logic; begin u1:adder4bit port map(a(3)=>bcd1(3),a(2)=>bcd1(2),a(1)=>bcd1(1),a(0)=>bcd1(0), b(3)=>bcd2(3),b(2)=>bcd2(2),b(1)=>bcd2(1),b(0)=>bcd2(0), carryin=>bcdcarryin,sum(3)=>s(3),sum(2)=>s(2),sum(1)=>s(1),sum(0)=>s(0),carryout=>c); K <= (s(3)and s(2))or(s(3)and s(1))or(c); x <= "0110" when k ='1' else "0000"; u2 :adder4bit port map(a(3)=>s(3),a(2)=>s(2),a(1)=>s(1),a(0)=>s(0),b(3)=>x(3),b(2)=>x(2),b(1)=>x(1),b(0)=>x(0),carryin=>'0', sum(3)=>bcdsum(3),sum(2)=>bcdsum(2),sum(1)=>bcdsum(1),sum(0)=>bcdsum(0), carryout=>bcdcarryout); end Behavioral;

2/10/07DSD,USIT,GGSIPU5 Waveform of bcd adder