M.Mohajjel

Structured Procedures Two basic structured procedure statements always initial All behavioral statements appear only inside these blocks Each always or initial block has a separate activity flow (concurrency) Start from simulation time 0 Digital System Design2

initial Statement Each block starts to execute concurrently at time 0 Each block executes exactly once during a simulation Digital System Design3 module stimulus; reg x,y, a,b, m; initial m = 1'b0; initial begin #5 a = 1'b1; #25 b = 1'b0; end initial begin #10 x = 1'b0; #25 y = 1'b1; end endmodule time statement executed 0 m = 1'b0; 5 a = 1'b1; 10 x = 1'b0; 30 b = 1'b0; 35 y = 1'b1;

Initializing variables Combined Declaration and Initialization reg clock=0; module adder (sum, co, a, b, ci); output reg [7:0] sum = 0; output reg co = 0; input [7:0] a, b; input ci; -- endmodule Digital System Design4

always Statement Starts at time 0 Executes the statements in the in a looping fashion Example Digital System Design5 module clock_gen (output reg clock); //Initialize clock at time zero initial clock = 1'b0; //Toggle clock every half-cycle (time period = 20) always #10 clock = ~clock; initial #1000 $finish; endmodule

Procedural Assignments Update values of register data types The value remains unchanged until another procedural assignment updates it Syntax: variable_lvalue = expression; variable_lvalue A register variable or a memory element A bit select of these variables (e.g., addr[0]) A part select of these variables (e.g., addr[31:16]) A concatenation of any of the above expressions Same as continues assignment Digital System Design6

Procedural Assignments (cont.) Blocking and non blocking Digital System Design7 reg a,b; initial begin a=0; b=0; a<=1; b=a; end //a=1 //b=0 reg a,b; initial begin a=0; b=0; a=1; b=a; end //a=1 //b=1

Nonblocking Assignments Model several concurrent data transfers Not dependent on the order in which the assignments are processed Example clock) begin reg1 <= in1; reg2 <= in2 ^ in3; reg3 <= reg1; //The old value of reg1 end Digital System Design8

Race conditions clock) a = b; clock) b = a; Digital System Design9 clock) a <= b; clock) b <= a;

Blocking assignment Digital System Design10 initial begin a=0; b=0; c=0; #2 a=1; #2 b=1; #2 c=1; end initial begin a=0; b=0; c=0; a = #2 1; #2 b = 1; #2 c = 1; end endmodule

Nonblocking assignment Digital System Design11 initial begin a=0; b=0; c=0; #2 a<=1; #2 b<=1; #2 c<=1; end initial begin a=0; b=0; c=0; a <= #2 1; #2 b = 1; #2 c = 1; end endmodule

Blocking & Nonblocking Digital System Design12 initial begin a=0; b=0; c=1'bx; a <= #2 1; #2 b <= 1; #2 c <= 1; c=0; end endmodule initial begin a=0; b=0; c=1'bx; a <= #2 1; #2 b <= 1; #2 c <= 1; #0 c=0; end

Timing Controls Delay-based Event-based Level-sensitive Digital System Design13

Delay-based Timing Controls Regular delay control Example parameter latency = 20; parameter delta = 2; reg x, y, z, p, q; initial begin x = 0; #10 y = 1; #latency z = 0; #(latency + delta) p = 1; #y x = x + 1; #(4:5:6) q = 0; end Digital System Design14

Delay-based Timing Controls(cont.) Intra-assignment delay control Example reg x, y, z; initial begin x = 0; z = 0; y = #5 x + z; end Digital System Design15 initial begin x = 0; z = 0; temp_xz = x + z; #5 y = temp_xz; end

Delay-based Timing Controls(cont.) Zero delay control Example initial begin x = 0; y = 0; end initial begin #0 x = 1; //zero delay control #0 y = 1; end Digital System Design16

Event-Based Timing Control Event change in the value on a register or a net utilized to trigger execution of statements Types of event-based timing control Regular event control Named event control Event OR control Digital System Design17

Event-Based Timing Control (cont.) Regular event control Statements can be executed on changes in: Signal value Positive transition of the signal value Negative transition of the signal value Digital System q = clock) q = clock) q = d; q clock) d;

Event-Based Timing Control (cont.) Named event control Keyword: event Digital System Design19 event received_data; clock) begin if(last_data_packet) ->received_data; end data_buf = {data_pkt[0], data_pkt[1], data_pkt[2], data_pkt[3]};

Event-Based Timing Control (cont.) Event OR Control (Sensitivity List) Multiple signals or events Syntax : or or … or "," (comma) operator instead of the or operator Example Digital System Design20 reset or clock or d) reset, clock, d) begin if (reset) q = 1'b0; else if(clock) q = d; end

Event-Based Timing Control (cont.) Event OR Control (Sensitivity List) Multiple signals or events Syntax : or or … or "," (comma) operator instead of the or operator Example Digital System Design21 reset or clock or d) begin if (reset) q = 1'b0; else if(clock) q = d; end clk, negedge reset) if(!reset) q <=0; else q <=d;

Event-Based Timing Control (cont.) Event OR Control (Sensitivity Example Digital System Design22 or b or c or d or e or f or g or h or p or m) begin out1 = a ? b+c : d+e; out2 = f ? g+h : p+m; end //Instead of the above method, symbol begin out1 = a ? b+c : d+e; out2 = f ? g+h : p+m; end

Level-Sensitive Timing Control wait for a certain condition to be true Keyword: wait Example Digital System Design23 always wait (count_enable) #20 count = count + 1; //difference? always (posedge count_enable) #20 count = count + 1;

Conditional Statements if(!lock) buffer = data; if(enable) out = in; if (number_queued < MAX_Q_DEPTH) begin data_queue = data; number_queued = number_queued + 1; end else $display("Queue Full. Try again"); if (alu_control == 0) y = x + z; else if(alu_control == 1) y = x - z; else if(alu_control == 2) y = x * z; else $display("Invalid ALU control signal"); Digital System Design24

Multiway Branching case statement Keywords : case, endcase, default Syntax Digital System Design25 case (expression) alternative1: statement1; alternative2: statement2; alternative3: statement3;... default: default_statement; endcase

Multiway Branching (cont.) case statement Example 1 Digital System Design26 //Execute statements based on the ALU control signal reg [1:0] alu_control;... case (alu_control) 2'd0 : y = x + z; 2'd1 : y = x - z; 2'd2 : y = x * z; default : $display("Invalid ALU control signal"); endcase

Multiway Branching (cont.) case statement Example 2 Digital System Design27 module mux4_to_1 (out, i0, i1, i2, i3, s1, s0); output out; input i0, i1, i2, i3; input s1, s0; reg out; or s0 or i0 or i1 or i2 or i3) case ({s1, s0}) 2'd0 : out = i0; 2'd1 : out = i1; 2'd2 : out = i2; 2'd3 : out = i3; default: $display("Invalid control signals"); endcase endmodule

Multiway Branching (cont.) case statement Example 3 Digital System Design28 module demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0); … or s0 or in) case ({s1, s0}) //Switch based on control signals 2'b00 : begin out0 = in; out1 = 1'bz; out2 = 1'bz; out3 = 1'bz; end 2'b01 : begin out0 = 1'bz; out1 = in; out2 = 1'bz; out3 = 1'bz; end 2'b10 : begin out0 = 1'bz; out1 = 1'bz; out2 = in; out3 = 1'bz; end 2'b11 : begin out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 = in; end 2'bx0, 2'bx1, 2'bxz, 2'bxx, 2'b0x, 2'b1x, 2'bzx : begin out0 = 1'bx; out1 = 1'bx; out2 = 1'bx; out3 = 1'bx; end 2'bz0, 2'bz1, 2'bzz, 2'b0z, 2'b1z : begin out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 = 1'bz; end default: $display("Unspecified control signals"); endcase endmodule

Multiway Branching (cont.) casez treats all z values as don't cares casex treats all x and z values as don't cares. Example Digital System Design29 reg [3:0] encoding; integer state; casex (encoding) //logic value x represents a don't care bit. 4'b1xxx : next_state = 3; 4'bx1xx : next_state = 2; 4'bxx1x : next_state = 1; 4'bxxx1 : next_state = 0; default : next_state = 0; endcase

4-bit Counter //4-bit Binary counter module counter(Q, clock, clear); // I/O ports output [3:0] Q; input clock, clear; //output defined as register reg [3:0] Q; posedge clear or negedge clock) begin if (clear) Q <= 4'd0; //Nonblocking assignments are recommended //for creating sequential logic such as flipflops else Q <= Q + 1;// Modulo 16 is not necessary because Q is a // 4-bit value and wraps around. end endmodule Digital System Design30

RAM Digital System Design31 module RAM_32bit(Data_in, Data_out, Address, clk, RW); input clk,RW; input [31:0] Data_in; input [3:0] Address; output reg [31:0] Data_out; reg [31:0] mem [15:0]; clk) begin if(RW) //read Data_out=mem[Address]; else mem[Address]=Data_in; end endmodule

Loops while Example 1 Digital System Design32 initial begin count = 0; while (count < 128) begin $display("Count = %d", count); count = count + 1; end

Loops while Example 2 Digital System Design33 clk) count2 = count2 + 1; initial begin while clk) count2 = count2 + 1; end

Loops (cont.) for Example integer count; initial for ( count=0; count < 128; count = count + 1) $display("Count = %d", count); Digital System Design34

Loops (cont.) repeat Example 1 integer count; initial begin count = 0; repeat(128) begin $display("Count = %d", count); count = count + 1; end Digital System Design35

Loops (cont.) repeat Example 2 Digital System Design36 module data_buffer(data_start, data, clock); … parameter cycles = 8; clock) begin if(data_start) begin i = 0; repeat(cycles) clock) buffer[i] = data; i = i + 1; end endmodule

Loops (cont.) forever disable Examples Digital System Design37 reg clock; initial begin clock = 1'b0; forever #10 clock = ~clock; end forever begin: my_loop #10; if(b==1'b1) disable my_loop; clock = ~clock; end $display("finish");

Sequential and Parallel Blocks Sequential blocks The statements are processed in the order they are specified. If delay or event control is specified, it is relative to the simulation time when the previous statement in the block completed execution Digital System Design38

Sequential and Parallel Blocks Parallel blocks fork and join Statements in a parallel block are executed concurrently Ordering of statements is controlled by the delay or event control assigned to each statement If delay or event control is specified, it is relative to the time the block was entered The order in which the statements are written in the block is not important reg x, y; reg [1:0] z, w; initial fork x = 1'b0; #5 y = 1'b1; #10 z = {x, y}; #20 w = {y, x}; join Digital System Design39

Sequential and Parallel Blocks Parallel blocks Race condition reg x, y; reg [1:0] z, w; initial fork x = 1'b0; y = 1'b1; z = {x, y}; w = {y, x}; join Digital System Design40

Nested blocks Sequential and parallel blocks can be mixed Example Digital System Design41 initial begin x = 1'b0; fork #5 y = 1'b1; #10 z = {x, y}; join #20 w = {y, x}; end

Named blocks Local variables Accessing by using hierarchical name Disabling Digital System Design42 module top; initial begin: block1 integer i; //top.block1.i... end initial fork: block2 reg i; //top.block2.i... join

Named blocks Example Digital System Design43 module test_forever; reg clock; initial begin clock = 1'b0; begin : my_loop integer i; forever begin #10 clock = ~clock; i=i+1; end $display("finish"); end initial begin test_forever.my_loop.i=0; #70 disable my_loop; $display("i=%d",my_loop.i); end endmodule

Reading assignment Chapter 7 Digital System Design44