PDR – Preliminary Design Review Gilad Tsoran Benny Fellman Advisor: Shahar Kvatinsky Winter 2013

Background Advances in memory technology inspire new architectures  Memristor based elements deliver large, fast, on die memory  Many ways to use this memory- “Memory Intensive Computing”

Current trend- MultiThreading Switch on Event (SoE) Fine grained (interleaved) SMT

Switch on Event  Advantages: −Less logic than SMT −Better utilization of pipeline than fine grained  Problem: −Flushing the pipe upon switch reduces performance and increases power  Solution: −CFMT architecture: keep pipe state nearby upon switch

Cache Miss Memory unit End of Memory Operation Concept Illustration

Project Goals  Analyze CFMT performance Requires:  Implementing on FPGA  Developing verification environment  Running benchmarks

Previous Project accomplishments  Simulation Level Verilog Implementation  Support for most of Alpha ISA  Initial analysis based on reduced benchmark running on simulation

High Level Design Pipe Line Execution Unit Controller (EUC) FetchDepend ancy check Addr calc. Exe. unit route int Write Back FP Mem Memristor Thread Memory Thread memory controller (TMC)Thread Switch Controller (TSC) Thread State Table (TST) Pipe control Decode

Development Environment  Design and simulation using ModelSim  Synthesis would be done with the FPGA specific tools  Analysis using Excel

Gantt Chart

Pipeline Stage Connector 11 Stage i Stage i+1 Memristor Memory En RST Select data