XC9500XL

XC9500XL Overview  Optimized for 3.3-V systems 0.35 micron FastFLASH technology 4 Layers of Metal compatible levels with 5.0/2.5V Reprogramming Endurance = 10,000 Charge Retention = 20 years  Meets performance requirements high f MAX = 200 MHz / fast t PD = 4 ns  Best ISP/JTAG support in industry  Best pinlocking in industry  Advanced packaging - New CSPs !

XC9500XL Architecture New extra-wide function block inputs – Uniform – Identical Functional Blocks – Identical Macrocells – Identical I/O pins – 5 ns pin-to-pin – 36 to 288 Macrocells (6400 gates) – Abundant Global Product Term Resources – Hysteresis on all inputs – Pullup/Bus Hold Option on Pins at power on – Great synthesis results – Best pinlocking results

FastCONNECT II Switch Matrix  Very High Speed Switch Matrix  2 nd Generation switch matrix  Used Fast Flash technology  Greater connectability for all signals  High routability at high utilization  Software delivers high speed automatically  Substantial power reduction

XC9500XL Feedback Paths  FastCONNECT  Pin  Local Macrocell FastCONNECT FB X Macrocell Pin feedback FastCONNECT feedback Local feedback

XC9500XL Function Block  Handles SDRAM address width with 54 inputs highest function block fan-in on fast CPLDs

XC9500XL Macrocell Local macrocell clock inversion control Flexible clocking and three-state control

Product Term Allocator Cascading 2 p-terms required here 5 available here 5 native p-terms 3 available here Total = 18 requires 2 cascade times added to t PD

Voltage Compatibility CORE LOGIC V CCINT = 3.3V V CCIO = 3.3V/2.5V Note: output p-channel gives full rail swing

Voltage Compatibility 2.5/3.3/5V 5V5V 3.3V Any 5V TTL device XC9500XL Any 2.5/3.3V device VCCIOVCCINT 5V5V 3.3V 2.5/3.3V 2.5V VCCINT

XC9500XL Voltage Compatibility Summary V IL V IH V OL V OH 5V CMOS 5V TTL 3.3V LVCMOS3.3V LVTTL2.5V Normal 3.3V XXX X X X X X X X X X X XX X X X EIA Standard Voltage Levels No Power Supply Sequencing Restriction

Input Signal Hysteresis V OH V OL 1.40V 1.45V V OUT V IN (VOLTS) 50 mV

Power Optimization  67% decrease from 5V CPLDs  Low power option per macrocell  Even lower power if I/Os swing 0-2.5V  FastCONNECT II lower power than XC9500  I/Os swing full VCCIO range with p-channel pullups (shuts off attached external logic)

ISP (In System Programming)  Original XC9500 JTAG and ISP instructions  New instruction: CLAMP permits pin by pin definition of logic level  Added S/W support with XACT M1.5  Same third party and ATE support package as XC9500 CPLDs (HP, GenRAD, Teradyne)

XC9500XL Fits In Industry Standard JTAG Chains XC9500XC4000EX uP DSP ASICXC9500 TDI TDO TMS TCK

Third Party ATE Support  Hewlett-Packard  Teradyne  Gen-RAD  Common Support for both Xilinx FPGAs and CPLDs.

Advanced CSP Packaging Supports high-growth market segments: Communications, Computers, Consumer Uses standard IR techniques for mounting to PC board

What’s Key for Pin-Locking  Must retain pinouts as the design evolves best done when the design software initially assigns pins different from pinout pre-assigning strong function of utilization in typical CPLD architectures result of both architecture and software strategy  Pin-locking is valuable eliminates or reduces PC Board rework minimizes time to market, saves money lowers designer frustration, risk

3 Keys to Pin-Locking Function Block FastCONNECT JTAG Global 3-State Global S/R Global Clocks Function Block Function Block Function Block Function Block Function Block Function Block  2 nd generation switch matrix:  Complete interconnect of all pins & blocks  All pin-to-pin paths at full speed Function Block ¶ Fully Populated Switch Matrix

3 Keys to Pin-Locking To FastCONNECT 2 3 Global 3-State Global Clocks I/O From FastCONNECT 54 Macrocell 1 AND Array Macrocell 18 Product Term Allocator Wide Function Block Fan-in Ë Flexible Macrocell Logic Allocation Ì

XC9500XL Supports Design Changes with Fixed Pinouts Design Change XC9500XL Feature èAdd another input FastCONNECT switch matrix pin or FB output with 100% connectivity èAdd more logic in XC9500 allows expansion the macrocell up to 90 P-terms èAdd additional input 54 total inputs are available connections to the FBplus FastCONNECT AND gate capability

Pin-Locking Compare Table Routability ExcellentGood*PoorGood Notes: * Decreases with density Xilinx XC9500XL Altera Max7KS Lattice 1K/2K/3K AMD Mach5 54 Yes 90 Yes 32 No 36 No 18/24 No 32 Fully populated switch Maximum pterms/Mcell Bi-directional individual product term allocation Function block fan-in

XC9500XL Other Features  Enhanced Data Security Features Read security bits prevent unauthorized reading Write security bits prevent accidental program/erase  Reduced power option per macrocell  3.3v/5v outputs  24 mA, 100% PCI compliant  Output Noise Reduction Slew rate control User programmable ground pin capability User Programmable Ground Pin User I/O Pin Ground Pin User I/O Pin Internal Logic Additional Ground Pin Lower ground inductance Reduce ground noise

54-input Function Block CLAMP instruction 2.5V/3.3V/5V I/O Capability Invertible Local & Global P- Term Clocks and OEs Input Hystersis +/-50mV Bus Hold Common ISP/JTAG Support for CPLDs/FPGAs Superior connectivity & performance Better control of board & system signals during ISP Easy multi-voltage interfacing Max number of clock & OE options Improves noise margin; better slow signal response Totally controlled board initialization One language supports all Xilinx products Xilinx FeatureSystem Designer Benefit XC9500XLSystem Designer’s CPLD

Xilinx CPLD Solutions t PD (pin-to-pin speed) t SU (set-up speed) I cc (supply current - typ) SpecificationXC9500-5XL*XC9500-5** t CO (clock-to-out speed) t OE (output enable speed) f SYS (system speed) Voltage 5ns* 3.7ns 11mA (Low Power) 18mA (Hi Perf) 3.5ns 4ns 178.6MHz 3.3V 5ns 4ns 30mA (Low Power) 50mA (Hi Perf) 4ns 5ns 100MHz 5V5V * XC9500XL also available in 4ns version ** New 5V speed specifications (as of 9/98) 5ns COMPARISON

XC9500XL Family 9536XL Macrocells Usable Gates t PD (ns) Packages QFPs 44PC 64VQ 48CS 44PC 64VQ 100TQ 48CS 100TQ 144TQ 144CS PQ 352BG 9572XL95144XL95288XL CSPs/BGA f MAX (MHz) TQ

CPLD Solution for PC99 SDRAM Controller Example Processor Personal Computer SpartanXL USB interface/ FireWire interface Device Bay Memory XC9500XL SDRAM Controller USB, FireWire interfaces USBFireWire

Challenges Facing the Design Engineer 100 MHz minimum speed Multiple SDRAM protocols Sufficient address width Clock flexibility Resources for future expansion Small package HDL entry Cost control Minimal programming overhead Board layout before design is complete Design time Three-state flexibility 3.3V/2.5V

Memory Interface Block Diagram SDRAMs Clock Write Reset Address[23:0] Address[11:0] CS RAS CAS WE Data[15:0] Complete SDRAM Controller in a single CPLD Microprocessor CPLD SDRAM Controller

SDRAM Interface Close-up Address[23:0] Data[15:0] ADDR[11:0] Clock Reset Write CS RAS CAS WE ADDR[23:12] ADDR[11:0] Refresh Counter Address Decode Chip Select Mode Register State Machine

Design in VHDL, Verilog, ABEL, etc. Submit design to WebFITTER Evaluate results CPLD Design on the Web  No software to load no user resources needed no license  WebFITTER software always current no upgrade CDs  Runs fast on network (minutes)

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SDRAM Controller Implementation in XC9500XL  Results for XC95144XL  Utilization 52% of capacity available for other logic  Speed faster than required for 133 MHz clock  Lowest-cost solution  Compare to chip sets and other CPLDs