C HAPTER S IX R EGISTERS AND C OUNTERS 1

A clocked sequential circuit consists of a group of flip-flops and combinational gates connected to form a feedback path. A circuit with flip-flops is considered a sequential circuit even in the absence of combinational gates. Circuits that include flip-flops are classified by the function they perform. Two such circuits are registers and counters. 2

A register is a group of flip-flops, each one of which is capable of storing one bit of information. An n-bit register consists of a group of n flip-flops. A register consists of a group of flip-flops together with gates that affect their operation. (they determine how the information is transferred into register). A counter is a special type of register that goes through a predetermined sequence of binary states. 3

4 Four-bit register

R EGISTER WITH PARALLEL LOAD The transfer of new information into a register is referred to as loading or updating the register. If all the bits of the register are loaded simultaneously with a common clock pulse, we say that the loading is done in parallel. 5 CLEAR or RESET. When CLEAR is 0 the flip flop is resetting independent of clock and D values. It is useful because in digital systems when the power is turned on the state of flip-flops is unknown. Direct input CLEAR can bring all flip-flops to the known starting state prior to the clock operation.

6 Four-bit register with parallel load Two channel mux

S HIFT R EGISTERS A register capable of shifting the binary information held in each cell to its neighboring cell in a selected direction is called a shift register. It consists of a chain of flip-flops in cascade, with the output of one flip-flop connected to the input of the next flip-flop. All flip-flops receive common clock pulses, which activate the shift of data from one stage to the next. We can control the shift operation by connecting (shift control) with the clock through an AND gate 7

8 Four-bit shift register input1011 F.F #1 (0)F.F #2 (0)F.F #3 (0)F.F #4 (0)

S ERIAL T RANSFER A digital system is said to operate in serial mode when information is transferred and manipulated one bit at a time. Information is transferred one bit at a time by shifting the bits out of the source register into the destination register. The serial transfer of information from register A to register B is done with shift registers where the SO of register A is connected to the SI of register B. 9

10 Serial transfer from register A to register B

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12 In the parallel mode, information is available from all bits of a register and all bits can be transferred simultaneously during one clock pulse. In the serial mode, the registers have a single serial input and a single serial output. The information is transferred one bit at a time while the registers are shifted in the same direction.

S ERIAL A DDITION 13

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U NIVERSAL SHIFT REGISTER A register capable of shifting in one direction only is a unidirectional shift register. A register capable of shifting in both direction is a bidirectional shift register. If the register has both shifts and parallel-load capabilities, it is referred to as a universal shift register. 16

The most general shift register has the following capabilities:  A clear control to clear the register to 0.  A clock input to synchronize the operation.  A shift-right control and the serial input & output lines associated with it.  A shift-left control and the serial input & output lines associated with it.  A parallel-load control and the n input lines associated with the parallel transfer.  n parallel output lines.  A control state that leaves the information in the register unchanged in response to the clock. 17

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R IPPLE COUNTERS (A SYNCHRONOUS ) A register that goes through a prescribed sequence of states upon the application of the clock pulses is called a counter. A counter that follows the binary number sequence is called a binary counter. An n -bit binary counter consists of n flip-flops and can count in binary from 0 to 2 n -1. Counters are available in two categories:  Ripple counters (Asynchronous)  Synchronous counters 20

B INARY RIPPLE COUNTER It consists of a series connection of complementing flip-flops ( T or D or JK ), with the output of each flip-flop connected to the C input of the next higher order flip-flop. The flip-flop holding the LSB receives the incoming count pulses. The T inputs of all the flip-flops are connected to logic 1, making each f-f complement if the clock input goes through a negative transition. For D f-f, the complemented output connected to the D input. 21

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BCD R IPPLE COUNTER (D ECADE C OUNTER ) A decimal counter follows a sequence of 10 states and returns to 0 after the count of 9. The BCD counter is a decade counter, since it counts from 0 to 9. 24

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To count in decimal from 0 to 99, we need a two- decade counter. To count in decimal from 0 to 999, we need a three-decade counter. 27

S YNCHRONOUS COUNTERS They are different from ripple counters in that clock pulses are applied to the input of all flip-flops. The decision whether a flip-flop is to be complemented is determined from the values of the data inputs. If T = 0 or J = K = 0, the flip-flop does not change state. If T = 1 or J = K = 1, the flip-flop complements. 28

29 A0A0 A1A1 A2A2 A3A3

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31 F LIP -F LOPS T Flip-Flop D = TQ’ + T’Q = T  Q JQ QK T DQ Q T D = JQ’ + K’Q TQ Q

U P - DOWN B INARY COUNTER The LSB is complemented with each pulse. A bit in any other position is complemented if all lower significant bits are equal to Up i/pDown i/pOperation 00No change 01Count down 10Count up 11Count up (up has higher priorty over the down)

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34 T Q1 = 1 T Q2 = Q’ 8 Q 1 T Q4 = Q 2 Q 1 T Q8 = Q 8 Q 1 + Q 4 Q 2 Q 1 Y = Q 8 Q 1 BCD C OUNTER

B INARY COUNTER WITH PARALLEL LOAD Counters in digital systems require a parallel- load capability for transferring an initial binary number into the counter prior to the count operation. 35

36 Asynchronous clear

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Using this counter as BCD counter 38 Initially the counter is cleared to 0 then put clear = count =1

The problems are : 6.2, 6.4, 6.8, , 6.7, 6.11, 6.12, , 6.22, 6.27,