© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.

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© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.
© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.
© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.
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© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust © 2008 Pearson Education Finite state machines

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed In this lecture we cover: Advanced FSM examples: Sequence detector example Vending machine example

Example 2: A Sequence Detector Design a sequence detector using D flip-flops and 8- to-1 multiplexers. The sequence detector outputs a 1 when exactly two of the last three inputs are 1. ▫ An input of produces the output of There is a one-bit serial input line and we will assume that initially no inputs have been seen. Note: the sequence detector cannot output a 1 until at least three inputs have been read.

The Sequence Detector  There are a total of eight sequences that the machine can observe:  000, 001, 010, 011, 100, 101, 110, 111  We will assume that state A is the initial state where no inputs have been fed into the machine.  In states B and C, only one input has been fed into the machine and therefore we cannot output a 1.

State Transition Diagram for the Sequence Detector

State Table and State Assignment for the Sequence Detector

Truth Table for the Sequence Detector

Creating the Circuit for the Sequence Detector  There needs to be one flip-flop for each state variable, so a total of three are needed.  Also, there are three next state functions and one output function, so four 8-to-1 multiplexers are needed.

Logic Diagram for the Sequence Detector

Example 3: A Vending Machine Controller  Design a vending machine controller using D-flip flops and a Programmable Logic Array (PLA).  The vending machine accepts three types of inputs: a nickel (5¢), a dime (10¢), or a quarter (25¢).  When the value of the total inserted coins equals or exceeds 20¢, the machine dispenses the merchandise, returns any excess change, and waits for the next transaction.

The Vending Machine Controller For simplicity, we will assume that if the machine currently has 15¢ and the user inserts a quarter, the merchandise will be dispensed, 15¢ will be returned, and the machine will keep 5¢ and await for more money. This way, we can use 4 states to represent all possible states: A (00) = 0¢C (10) = 10¢ B (01) = 5¢D (11) = 15¢ We will need two bits each to uniquely encode all possible states as well as inputs.

State Transition Diagram for the Vending Machine Input / Output 2 Output 1 Output 0 Input = Nickel | Dime | Quarter Output 2 = 1|0 = Dispense / Do not dispense merchandise Output 1 = 1|0 = Return / Do not return a nickel in change Output 0 = 1|0 = Return / Do not return a dime in change

State Table and State Assignment for the Vending Machine Present State = s n Input = x n Output = z n

Truth Table for the Vending Machine s1s1 s2s2 x1x1 x0x0 s1s1 s0s0 z2z2 z1z1 z0z ddddd ddddd ddddd ddddd For the FSM circuit, we will need: Two D flip-flops to represent the two state bits. PLA that takes four inputs (two for the present state bits and two for the coin bits) and has five outputs (two for the next state bits and three for the dispense and return bits).

Logic Design for the Vending Machine Assumes the clock input is asserted only on an event such as the user inserting a coin into the machine. 5x5 PLA QDs0QDs0 QDs1QDs1 CLK z2z2 z1z1 z0z0 x1x1 x0x0

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Next lecture covers LCL presentation 4: Mealy FSM Moore FSM