Trigger Meeting: Greg Iles5 March The APV Emulator (APVE) Task 1. –The APV25 has a 10 event buffer in de-convolution mode. –Readout of an event = 7  s –Triggers arrive in a Poisson distribution with mean period = 10  s. –Finite buffer + Random triggers => Possibility of buffer overflow –OVERFLOW => DEAD TRACKER (APV reset required) Task 2. –The FED provides the median APV pipeline address of all its channels and compares it against a “golden” pipeline address provided by the APVE. APVE protects against buffer overflow APVE detects loss of sync in a Tracker partition What does the APVE do & why ?

Trigger Meeting: Greg Iles5 March Tracker APV in deconvolution mode What does APVE do & why ? Primary task: Preventing buffer overflow in APVs –Its takes too long to send a ‘buffers full’ signal from APVs in the tracker to Trigger Control System (TCS). –Therefore require an APV close to the TCS. Secondary task: Synchronisation check –All APV data frames include the memory cell (pipeline) address used to store the L1A data in the APV. –The pipeline address is sent to all FEDs to ensure that all APVs are in-sync. APVE 1: Full 2: Full 3: Empty 10: Empty Data frame TCS: Inhibit L1A ? Reset and L1A Busy FED: Data OK? Pipeline address (min period = 75ns) (period = 7000ns)

Trigger Meeting: Greg Iles5 March How does APVE work ? L1A Throttle –A counter keeps track of the number of filled APV buffers. L1A => INCREMENTS counter. Output frame => DECREMENTS the counter. Reset => CLEARS the counter. APVE must receive the same L1As and Resets as APVs within the Tracker or System fails –When the counter reaches preset values it asserts Warn followed by Busy. Synchronisation check –Header on APV data frame provides pipeline address Real APV25 Buffer counter L1A APV data frame Pipeline address to FEDs Busy DECREMENT Reset CLEAR Frame output signal Assert busy ? Header recognition APVE INCREMENT

Trigger Meeting: Greg Iles5 March Task 1: L1A Throttle Timing critical –Set by control loop from L1A inhibit gate within Global or Local TCS to APVE and back again. –Want to assert busy < 75ns) –Alternatively we lose an event buffer location in the APV for every 75ns delay. Loss of buffers increases dead time. Require fast access to GTCS/LTCS to receive L1A/RESET and send Fast Control signals. –TCS prefers a single set of Fast Control signals from the Tracker. Fast Merge Module (FMM) signals to go via APVE L1A & RESET Inhibit gate (inside TCS) APVE Buffers Full ? L1A & RESET BUSY

Trigger Meeting: Greg Iles5 March Deadtime

Trigger Meeting: Greg Iles5 March Control structure WARNING –Timing structure of L1As and Resets received by the APVE and the APVs within the Tracker must be identical. –How are resets issued by the TCS transformed into ‘101’ resets for the APV. Also relevant for ‘11’ calibrates. –The APVE will NOT operate if the TTCvi is used as a source of Resets & L1As. APVETTCvi Fast control APV GTCSLTCS TTCex TTCtx FEC CCU Ring FED FMM Fast Merge Module Pipeline address Reset & L1As ? Applying timing constraints to control structure –At present envisage that APVE receives L1A and Reset from both Global and Local TCS.

Trigger Meeting: Greg Iles5 March Current progress Development system built and tested. –Fast Control functions (i.e. busy, warn and out-of-sync). –Programmable (i.e busy asserted when ‘X’ many APV buffers remain empty. –History of signals recorded busy, warn, out-of-sync (i.e. when asserted, when negated) for ‘X’ many occasions. Total time asserted for busy, warn, and out-of-sync. –Interfaces such VME, Wishbone and I2C interface –TCS system implemented for testing. APV Trig & ResetClk FPGA

Reset Test Signal Post TCS, T1 to APV APV Output Busy Warn Reset GTCS Trigger before GTCS inhibit Time penalty incurred in the FPGA to distinguish triggers, '1' from resets, '101‘ and calibrates, '11‘, unless we receive trigger and reset signals separately. ‘101’ reset‘1’ trigger inhibit blocks trigger first tick after APV reset busy asserted warn asserted

End of reset period Busy asserted after 8 triggers. Warn asserted after 5 triggers. APV ready to receive trigger ‘1’ trigger Test Signal Post TCS, T1 to APV APV Output Busy Warn Reset GTCS Trigger before GTCS inhibit

Buffer empties Busy negated when an APV buffer empties, providing space for another event to be stored. It is asserted once more after a further trigger is sent to the APV. ‘1’ trigger APV frame digital header Test Signal Post TCS, T1 to APV APV Output Busy Warn Reset GTCS Trigger before GTCS inhibit

Trigger Meeting: Greg Iles5 March Future.... Simulate APV in real time VHDL code to simulate the APV in real time written and tested on ModelSim (VHDL logic simulation package), but not downloaded into an FPGA. An FPGA is sufficiently fast The APV pipeline logic, a possible obstacle to FPGA implementation, has been tested in a Xilinx Spartan and sufficiently large At a size of 200k gates the design is too big for our Spartan-2 (100k gates), but will fit in a Virtex-2.

Trigger Meeting: Greg Iles5 March Task 2: Sync (global) Task 2. –FED detects individual APVs losing sync –If more than 65 (?) APVs out of sync FED can generate the wrong pipeline address Incorrect data to the DAQ. –Should happen very rarely How important is getting pipeline address to the FED? APVE detects loss of sync in a Tracker partition

Trigger Meeting: Greg Iles5 March Pipeline address via network At present –Check data after it has been sent to DAQ at a frequency of every few seconds and in software. Cons... –Requires lots of software and the pipeline address travels a complex route to FED. APVE Crate CPUCPU APVEAPVE APVEAPVE APVEAPVE APVEAPVE FED Crate CPUCPU FEDFED FEDFED FEDFED CPUCPU FEDFED FEDFED FEDFED x10 (ish) x20

Trigger Meeting: Greg Iles5 March Pipeline address via serial link Possibly..... –Direct serial link (optical) to each FED crate. –Pipeline address distributed to FEDs via single trace on VME back-plane. Cons... –Additional hardware which needs to be designed built and tested. –Reliability & maintenance for duration of LHC. APVE Crate APVEAPVE APVEAPVE APVEAPVE APVEAPVE FED Crate APVPAPVP FEDFED FEDFED CPUCPU FEDFED FEDFED FEDFED x10 (ish) CPUCPU CPUCPU APVPAPVP

Trigger Meeting: Greg Iles5 March Outstanding issues Where do we get L1A and Reset from, if not LTCS and GTCS ? –If not LTCS & GTCS what is the time penalty of obtaining these signals further down the command chain? Where does merge of fast feedback signals take place, if at all ? –APVE needs to be the last stage in this process, or very near it because timing critical. –What is the time penalty imposed by going through FMM? –At present APVE design assumes it is after FMM module and has 4 inputs (Ready/Error/Busy, Warn and Out-Of-Sync) that are OR’ed with APVE fast feedback signals. How do we get pipeline address to the FEDs ? –At present intend to check data after it has been sent to DAQ at a frequency of every few seconds and in software. –Serial link to each FED crate VME bus is possibly a simpler, more robust option, but more awkward to implement.

Trigger Meeting: Greg Iles5 March Conclusions Need to finalise location of APVE in command (RESET/L1A) and fast feedback (BUSY/WARN etc.) control structure. When details finalised we will be able to finish board schematics, manufacture and test APVE. At the beginning we envisage 4 VME boards, one for each partition located in the Global Trigger rack.

Trigger Meeting: Greg Iles5 March APVE IO FPGA Global TCS, Reset/L1A Global TCS Fast Control FMM, Fast Control Local TCS, Reset/L1A Local TCS Fast Control LHC Clock VME, A24/D16 Perhaps also A fibre optic serial links to each FED crate to deliver the pipeline address (approx 10 per APVE)