LECTURE IV MODELSIM

Go to the link listed below for a demonstration of how to begin working with Modelsim. The video shows you how to write a Verilog project which creates an Inverter logic gate, compiles the program and then simulates it. Note that there are a variety of ways to accomplish the same thing in Verilog. For example, his module statement could have been placed on a single line. Either way works. You will find that this is the often the case in Verilog.

Try running the sample project that was written in Lecture 3: module Simple_Circuit (A,B,C,D,E); outputD,E; inputA,B,C; wirew1; andG1 (w1,A,B); // Optional gate instance name notG2 (E,C); orG3 (D,w1,E); endmodule

1) Begin by opening Modelsim 2) Click "Jumpstart" in the opening box 3) Click on "Create a Project" 4) Give the project a name and click "OK" 5) Click "Create New File" 6) Give the file a name (I usually use the same one used for the project name. VERY IMPORTANT: Under "Add file as type" click the arrow and select "Verilog" and now click "OK”.

7) Now click on the "Close" button in the "Add items to the Project" box 8) You should now see a.v file in the upper left corner 9) Right click in this file and then click "Edit" 10) You should now see the text editor box to the right. Either rewrite the project mentioned above or cut and paste it into this area. 11) IMPORTANT: You must now save your project before proceeding! Click on the floppy disc icon to do so. (Don't know what a floppy disc is? Ask your parents.)

12) AFTER saving the file, you are now ready compile the project. 13) Right click on the file and hover over "Compile". Click on Compile Selected" 14) If you have written your project correctly, a check mark will appear after the file name and a message stating that the compile was successful will appear in the Transcript box. If these two things don't happen, a compiler error has occurred. To get a hint as to what is wrong, right click on the file name, hover over "Compile" and click on "Compile Report". A message will appear giving you some indication as to what caused the project to fail to compile. Note: sometimes these messages are quite clear and point directly to the problem and then there are other times when they seem to make no sense. Good luck. (A good idea is to very carefully examine your syntax)

15) Once you have successfully compiled your project you are now ready to simulate it. 16) Right click on the project name in the Library and click on Simulate. 17) Now click on Wave (lower center of screen). Notice the changes on the screen. You should see a blank area called "Wave Default" and to the right of that, something that looks like a logic analyzer with a time scale at the bottom. ( If you don't know what a logic analyzer is, try Google.) 18) Click and drag the inputs and outputs that you want to observe from the "Objects" box to the "Wave- Default" box.

19) Now you need to set the inputs to some initial value. Do this by right clicking on one of the inputs and then click on "Force". find the "Value" box and replace its contents with either a 1 or a 0. Repeat for the rest of the Inputs. 20) Once you have set all of the inputs to the desired values, you can now run the simulation. Do so by clicking on the "Run" box located at the top of the screen just right of the "Run Length" box which should read "100 ns". 21) Force the inputs to different values and click on the "Run" box again. You should observe a different waveform which corresponds to the values you forced the inputs to be.