System IC Design Lab. Dongguk University 1 Study of CERN for the ALICE ITS upgrade Study of CERN for the ALICE ITS upgrade KIM,D.H., KWON,Y.,SONG,M.K. Department of Semiconductor Science, Dongguk Univ. for the ALICE collaboration. Department of Physics, Yonsei Univ. for the ALICE collaboration.

System IC Design Lab. Dongguk University 2 I.Introduction II.Explorer – study of pixel sensor III.pALPIDE – study of front-end and readout IV.Conclusion V.Appendix – work for ITS upgrade

System IC Design Lab. Dongguk University 3 I. Introduction - ALICE Inner Tracking System at present 2 layers of hybrid pixels (SPD) 2 layers of silicon drift detector (SDD) 2 layers of silicon strips (SSD)

System IC Design Lab. Dongguk University 4 I. Introduction - ITS upgrade – 7 layers Inner BarrelOuter Barrel Layer# Radial position (mm) Length in z(mm) Nr. Of staves Nr. Of chips/staves95698 Nr. Of chips/layer Material thickness~0.3% X 0 ~0.8% X 0 Throughput< 200 Mbit / sec*cm2< 6 Mbit / sec*cm2

System IC Design Lab. Dongguk University 5 I. Introduction - Design specifications for PIXEL Chip ParameterInner BarrelOuter Barrel Silicon thickness50 μm Chip Size 15 mm x 30 mm Pixel Size (r- ϕ ) μm20-50 μm Readout Time< 30 μs Power density<< 300 mW / cm 2 < 100 mW / cm 2 Hit density< 115 / cm 2 < 1.5 / cm 2 Radiation Load (TID)< 700 krad< 10 krad 1 MeV neq fluency< 1013 cm -2 < 3x1010 cm -2 Data throughputs (*)0.6 Gbit/s per chip7 Mbit/s per chip (*) Assumptions: Nr of bits to code a hit: 35 Fake hit: 10-5 /event

System IC Design Lab. Dongguk University 6 I. Introduction - Technology Commercial CMOS Imaging Sensor (CIS) High resistivity epi layer Deep p-well Physical gate oxide thickness: 3 nm Metal Option 6ML1 5 routing metals + 1 last metal for power busses

System IC Design Lab. Dongguk University 7 II. Explorer - PIXEL SENSOR OPTIMIZATION II. Explorer - PIXEL SENSOR OPTIMIZATION

System IC Design Lab. Dongguk University 8 II. Explorer - Prototype July 2012 submission: Explorer-0  Analog readout for pixel characterization  Readout time decoupled from integration time  Possibility to reverse bias the substrate  Sequential readout with correlated double sampling  Contains two 1.8x1.8mm 2 matrices of 20x20 and 30x30 micron pixels with different geometries PULSED ROWS

System IC Design Lab. Dongguk University 9 II. Explorer - Charge collection  Minimum Ionizing Particle (MIP) creates ~ 60 e/h pairs per micron of silicon traversed (in a thin layer)  Example for 18 μm thick layer: 1200 e => 0.17 fC  Advantages of having collection by drift:  Tolerance to non ionizing radiation (less trapping probability)  Reduction of the cluster size (less charge sharing) DiffusionDrift ForceCharge carrier concentration gradient Electric field Collection time ~ s< s Minority charge carrier path length LongShort

System IC Design Lab. Dongguk University 10 II. Explorer - Explorer - Collection electrode layout Sectornwell widthShapeSide lengthSpacingnwell areaCharacteristic 12 μmOctagon0.83 μm0.00 μm3.31 μm 2 Smallest diode, lower collection eff. 2 & 83 μmOctagon1.24 μm0.00 μm7.46 μm 2 Intermediate performance, S/N lower 34 μmOctagon1.66 μm0.00 μm13.25 μm 2 Lager diode, no spacing, more noise 43 μmSquare3.00 μm0.00 μm9.00 μm 2 Performance similar to sector 2 53 μmOctagon1.24 μm0.60 μm7.46 μm 2 Small spacing, lower efficiency 6 & 93 μmOctagon1.25 μm 1.04 μm7.46 μm 2 Better S/N increasing spacing 72 μmOctagon0.83 μm1.54 μm3.31 μm 2 Better collection eff., better S/N NMOS transistors in sectors 7, 8 and 9 are in a triple well. nwell – spacing – pwell contact

System IC Design Lab. Dongguk University 11 II. Explorer - Block diagram analog read-out for characterization studies readout time decoupled from integration time double readout in CDS mode RESET STORE1 STORE2 Pixel circuit two independent analog memory cells, signal stored just after RESET and at the end of integration cycle rowSelect VDD + VSS + columnSelect SEQUENCER VPULSE … analog biases BIAS pixels read serially PULSER Periphery column select OUT

System IC Design Lab. Dongguk University 12 II. Explorer - Explorer- circuit Features: Serial readout. Substrate bias < 0 V. Tunable charge integration time.

System IC Design Lab. Dongguk University 13 III. pALPIDE - FRONT-END and READOUT III. pALPIDE - FRONT-END and READOUT

System IC Design Lab. Dongguk University 14 III. pALPIDE - pALPIDE: prototype ALice PIxel DEtector Priority encoder Pixel front-end 512 STATE RESET 512 STATE RESET VALID SELECT ADDR 10 VALID SELECT ADDR Periphery Data Bias Clock Control + trigger Pulser Pixel front-end Priority encoder Pixel front-end 512 STATE RESET 512 STATE RESET Pixel front-end low power in-pixel discriminator current comparator (bias of ~20 nA) storage element for hit information in-matrix address encoder tree structure to decrease capacitive load of lines outputs pixel address and resets pixel storage element loss-less data compression de-randomizing circuit compresses cluster information in the column multi-event memory

System IC Design Lab. Dongguk University 15 III. pALPIDE - IN-PIXEL HIT DISCRIMINATION Low Power Analog Front End (Power < 50 nW/pixel) based on a single stage amplifier/current comparator. Data driven readout of the pixel matrix, only zero-suppressed data are transferred to the periphery. Dynamic Memory Cell, Storage capacitor instead of SR-latch to save space.

System IC Design Lab. Dongguk University 16 III. pALPIDE - Front-End principle Ibias(20nA) Ithr(0.5nA) Idb(10nA) Low Power Analog Front End based on an weak inversion operation mode.  except current source transistor (M0, M4, M6)

System IC Design Lab. Dongguk University 17 III. pALPIDE - Front-End principle v in vxvx v source v curfeed v out v outb

System IC Design Lab. Dongguk University 18 III. pALPIDE - Front-End output example Front End output with a bias current of 20 nA

System IC Design Lab. Dongguk University 19 III. pALPIDE - Front-End output example Minimum detectable charge definition Memory state (V) Qin (electrons) Minimum detectable charge as a function of the bias current Cd = 1 fF Ith = 0.5 nA Ileak = 5 pA (nominal 20 nA condition)

System IC Design Lab. Dongguk University 20 III. pALPIDE - Priority Encoder readout valid select a[0] a[1] ADDR[0:1]ADDR[2:3] VALID SELECT v[0] v[1] v[2] v[3] sel[0] sel[1] sel[2] sel[3] Periphery logic CLOCK valid select a[0] a[1] v[0] v[1] v[2] v[3] sel[0] sel[1] sel[2] sel[3] valid select a[0] a[1] v[0] v[1] v[2] v[3] sel[0] sel[1] sel[2] sel[3] valid select a[0] a[1] v[0] v[1] v[2] v[3] sel[0] sel[1] sel[2] sel[3] valid select a[0] a[1] v[0] v[1] v[2] v[3] sel[0] sel[1] sel[2] sel[3] TRIGGER  hierarchical readout  4 inputs basic block repeated to create a larger encoder  1 pixel read per clock cycle  forward path (address encoder) in gray  feed-back path (pixel reset) in red  asynchronous (combinatorial) logic  clock only to periphery, synchronous select only to hit pixels PIXEL COLUMN

System IC Design Lab. Dongguk University 21 III. pALPIDE - Layout of pALPIDE Pixel Matrix: sensitive area Chip size: 30 mm x 15 mm Pixel size: 28 μm x 28 μm 1024 Columns x 512 Rows Periphery circuit ( DAC, PADs, periphery readout logic, etc) PRIORITY ENCODER FRONT-END CollectionDiode StateMemory PIXEL LOGIC I can‘t see information of Digital circuit  PRIORITY ENCODER, periphery readout logic, etc

System IC Design Lab. Dongguk University 22 IV. Conclusion Green : complete understanding Explorer pALPIDE PIXEL Readout Front-End Readout Periphery Charge collection - Diffusion, Drift Design of collection electrode - shape, nwell area, spacing … Analysis about characteristic of each collection electrode Readout circuit Rolling shutter architecture Sequential readout with correlated double sampling Asynchronous comparator - operation principle,weak inversion, noise analysis Memory Pixel Logic circuit Priority Encoder - Asynchronous logic, implement Periphery readout logic - synchronous select only to hit pixels, implement DAC & ADC PLL PAD etc

System IC Design Lab. Dongguk University 23 IV. Conclusion Blue : weak understanding Explorer pALPIDE PIXEL Readout Front-End Readout Periphery Charge collection - Diffusion, Drift Design of collection electrode - shape, nwell area, spacing … Analysis about characteristic of each collection electrode Readout circuit Rolling shutter architecture Sequential readout with correlated double sampling Asynchronous comparator - operation principle,weak inversion, noise analysis Memory Pixel Logic circuit Priority Encoder - Asynchronous logic, implement Periphery readout logic - synchronous select only to hit pixels, implement DAC & ADC PLL PAD etc

System IC Design Lab. Dongguk University 24 IV. Conclusion Red : didn’t understand Explorer pALPIDE PIXEL Readout Front-End Readout Periphery Charge collection - Diffusion, Drift Design of collection electrode - shape, nwell area, spacing … Analysis about characteristic of each collection electrode Readout circuit Rolling shutter architecture Sequential readout with correlated double sampling Asynchronous comparator - operation principle,weak inversion, noise analysis Memory Pixel Logic circuit Priority Encoder - Asynchronous logic, implement Periphery readout logic - synchronous select only to hit pixels, implement DAC & ADC PLL PAD etc

System IC Design Lab. Dongguk University 25 Study of pixel Studied the collection electrode. (shape, size, layout, etc)  But it was studied by Explorer result. So it needs to implement for more detailed analysis. Analog readout circuit Studied the Front-end circuit. (operation principle)  But it was studied by simulation result. It needs to study an weak inversion operation mode in analog circuit for more detailed analysis of front-end circuit. Digital readout circuit  I didn’t have a chance for study digital readout circuit. IV. Conclusion IV. Conclusion

System IC Design Lab. Dongguk University 26 Thank you

System IC Design Lab. Dongguk University 27 V. Appendix DAC - List of Voltage and Current DACs Voltage DACCurrent DAC Resolution8bit TypeResistorpMOS Output/unitcolu mn 6EA 1) V CASP 2) V CASN 3) V RESET 4) V PULSE _ LOW 5) V PULSE _ HIGH 6) V AUX 5EA 1) I BIAS 2) I THR 3) I DB 4) I AUX 1 5) I AUX 2

System IC Design Lab. Dongguk University 28 V. Appendix DAC – Voltage DAC VCASPVCASNVRESET VPLSE_L OW VPLSE_HI GH VRESET mV V VREF AVSS Block diagram & Simulation result

System IC Design Lab. Dongguk University 29 V. Appendix DAC – Monitoring & Overriding mode Voltage DAC InputOperation SWCNTL_Vxxx Only one SWCNTL_Vxxx can be “1” 0To matrix (normal operation) 1To DACMONV SWCNTL_DACMONV common signal for all voltage DACs 0Monitoring 1Overriding  Monitoring mode, external circuit requirement: o Measure a voltage value between 0 and VREF with a 10 bit resolution. o Read-out circuit with a high input impedance (R in > 1 MΩ).  Overriding mode, external circuit requirement: o Set a voltage value on a high impedance net between 0 and VREF with a 8 bit resolution

System IC Design Lab. Dongguk University 30 V. Appendix DAC – Monitoring & Overriding mode Current DAC - Overriding reduction current mirror = 10 : 1 for bias currents 11 : 1 for IREF - Monitoring amplification current mirror = 1 : 10 Monitor or ove rride a current i n the 0 to 200 µ A range PAD 1 : 10 AVSS  Monitoring mode, external circuit requirement: o Measure a current between 0 and 200 µ A o Suggested load for the current measurement: ~ 5 kΩ (shunt between DACMONI and AVSS)  Overriding mode, external circuit requirement: o Set a current between 0 and 200 µ A with a 9 bit resolution. o The current can be set with a tunable resistor between 5 kΩ and 5 MΩ (shunt between DACMONI and AVSS)

System IC Design Lab. Dongguk University 31 V. Appendix PIXEL– Input capacitance Routing capacitance Collection diode capacitance Reset diode capacitance

System IC Design Lab. Dongguk University 32 V. Appendix PIXEL– Input capacitance If –Av is 1, Cm = 0 Input capacitance is can be compensated. Routing capacitance

System IC Design Lab. Dongguk University 33 V. Appendix PIXEL– Input capacitance Routing capacitance  pALPIDE front-end circuit instead of Special source Follower to decrease input capacitance