1 Lecture #11 EGR 277 – Digital Logic Ch. 5 - Synchronous Sequential Logic There are two primary classifications of logic circuits: 1.Combinational logic circuits Chapters 1 – 4 dealt with combinational logic circuits Circuits of this type have outputs that are functions of the inputs (illustrated below) The order in which the inputs are applied is not important. Reading Assignment: Chapter 5 in Digital Design, 3 rd Edition by Mano

2 Lecture #11 EGR 277 – Digital Logic 2.Sequential logic circuits Chapters 5-6 deal with sequential logic circuits Circuits of this type have outputs that are functions of both inputs and previous outputs (illustrated below) Sequential circuits contain some type of memory elements. As an example, a counter must “remember” that its previous output was 6 in order to produce its new output 7. Combinational logic circuits have no capability for memory. Sequential logic circuits typically also include some combinational logic components. Combinational Logic Inputs Outputs = f(inputs + past outputs) Memory Sequential Logic Circuit

3 Lecture #11 EGR 277 – Digital Logic There are two main types of sequential circuits: 1)Synchronous Sequential Circuits (also called Clock Sequential Circuits) –All signals are synchronized to some “master clock” –The memory devices respond only when activated by the master clock –The most common memory device: the flip-flop –This course will primarily focus on this type of sequential circuit –Circuits can be designed using systematic methods such as the excitation table method and the state equation method 2)Asynchronous Sequential Circuits –Outputs depend solely on the order in which the inputs change, so timing is critical. –Based on time-delay devices –The design methods used for synchronous sequential circuits do not apply to asynchronous circuits. As a result, design is difficult and not well defined.

4 Lecture #11 EGR 277 – Digital Logic Flip-flops and latches Binary memory cell capable of storing 1 bit or information (either stores a 0 or a 1) Have two outputs, Q and Q’ Q = binary state = present state = value stored Maintain the present state Q indefinitely until inputs instruct it to change Flip-flops and latches behave as described above but have one key difference: –A latch can change states whenever the input signals change –A flip-flop has a clocked input and can only change at certain times specified by the type of clocking. So a flip-flop could be called a clocked latch. See below. S R Q Q’ SR Latch S R Q Q’ SR Flip-Flop Clock input

5 Lecture #11 EGR 277 – Digital Logic Basic RS (or SR) Latch Operation A simple SR latch can be constructed using either two NAND gates or two NOR gates with feedback connections. The NOR circuit is shown below. Determine the truth table for the RS latch shown.

6 Lecture #11 EGR 277 – Digital Logic Discuss the operation of the simple clocked RS latch shown below. Q Q R S Clock A simple clocked RS latch

7 Lecture #11 EGR 277 – Digital Logic Flip – flops - There are 4 primary types of flip-flops: SR flip-flop D flip-flop JK flip-flop T flip-flop For each type, show the truth table and symbol. Show how to create a D flip-flop from an SR flip-flop or a JK flip-flop. Show how to create a T flip-flop from a JK flip-flop.

8 Lecture #11 EGR 277 – Digital Logic Triggering of flip-flops A trigger is a momentary change in the input clock signal which allows for a possible change in the state of the flip-flop. Flip-flops are typically triggered by pulse transitions, using either the rising (positive) edge or the falling (negative) edge of the clock waveform (see below).

9 Lecture #11 EGR 277 – Digital Logic There are 3 common types of triggering: 1.Positive-edge triggering – the flip-flop output can only change on the positive edges of the clock 2.Negative-edge triggering – the flip-flop output can only change on the negative edges of the clock 3.Master-slave (or pulse triggered) – the flip-flop “reads” the input values on the positive edge of the clock, but does not allow the output to respond until the negative edges of the clock Different symbols are sometimes used for each type of triggering (not universally recognized) as shown: J K Q Q Positive-edge triggered- Clock JK Flip-flop J K Q Q Negative-edge triggered Clock JK Flip-flop J K Q Q Master-slave Clock JK Flip-flop C

10 Lecture #11 EGR 277 – Digital Logic 3.Master-slave (or pulse triggered) – the flip-flop “reads” the input values on the positive edge of the clock, but does not allow the output to respond until the negative edges of the clock Show how to create a Master-slave JK flip-flop using two positive-edge triggered JK flip-flops. Discuss the “Data Lockout” feature sometimes available with master-slave flip- flops.

11 Lecture #11 EGR 277 – Digital Logic Example: Given J, K, and Clock input waveforms, sketch the output Q for a JK flip- flop if each flip-flop is initially an the type of triggering is: a)positive-edge triggering (labeled as Q1) b)negative-edge triggering (labeled as Q2) c)master-slave triggering (labeled as Q3)

12 Lecture #11 EGR 277 – Digital Logic Asynchronous (Direct) Inputs Two inputs are commonly available that can be used to initialize a flip-flop independently of the clock: PRESET – used to initialize the flip-flop to Q = 1 CLEAR – used to initialize the flip-flop to Q = 0 Sketch a JK flip-flop with active-LOW inputs for PRESET and CLEAR.

13 Lecture #11 EGR 277 – Digital Logic Example: Given J, K, PRESET, CLEAR and Clock input waveforms for a negative- edge triggered JK flip-flop, sketch Q. Assume that PRESET and CLEAR are active- LOW inputs.

14 Lecture #11 EGR 277 – Digital Logic Commercially available flip-flop IC’s. A few are listed below and ORCAD 9.2 symbols are shown below also Dual JK Master-Slave Flip-flop with CLEAR 7473A Dual JK Negative-Edge Triggered Flip-flop with CLEAR 7474 Dual D Positive-Edge Triggered Flip-flop with PRESET and CLEAR 7476B Dual JK Master-Slave Flip-flop with PRESET and CLEAR Dual D Positive-Edge Triggered Flip-flop with PRESET and CLEAR Dual JK Master-Slave Flip-flop with PRESET and CLEAR (with Data Lockout) Quadruple S’-R’ Latch