1 COMP541 Sequential Circuits Montek Singh Feb 1, 2007

2Administrative  Advance Notice Test: Week of Feb Test: Week of Feb Covers material through Thursday 2/15 Covers material through Thursday 2/15  Short review session on 2/15 in class

3Topics  Sequential Circuits Latches Latches Flip Flops Flip Flops  Verilog for sequential design

4 Sequential Circuits  State of system is info stored  That, and inputs, determine outputs

5 Types of Sequential Circuits  Synchronous State changes synchronized by one or more clocks State changes synchronized by one or more clocks  Asynchronous Changes occur independently Changes occur independently

6 Clocking of Synchronous  Changes enabled by clock

7Comparison  Synchronous Easier to analyze because can factor out gate delays Easier to analyze because can factor out gate delays Set clock so changes occur before next clock pulse Set clock so changes occur before next clock pulse  Asynchronous Potentially faster Potentially faster Harder to analyze (more subtle, but more powerful!) Harder to analyze (more subtle, but more powerful!)  Most of my research!  Will look mostly at synchronous

8 Basic Storage  Apply low or high for longer than t pd  Feedback will hold value

9 SR (set-reset) Latches  Basic storage made from gates S & R both 0 in “resting” state Have to keep both from 1 at same time

10Operation

11 Latch Latch  Similar – made from NANDs

12 Add Control Input  Gates when state can change  Is there latch w/ no illegal state?

13 D-type Latch  No illegal state

14 Transparency of latches  As long as C (the control ) is high, state can change This is called transparency This is called transparency  What’s problem with that?

15 Effects of Transparency  Output of latch may feed back May cause further state changes May cause further state changes Behavior depends on actual gate delays Behavior depends on actual gate delays  Want to change latch state only once Behavior should depend only on logical values Behavior should depend only on logical values

16 Solution to Transparency: Flip-Flops  Flip-Flops: Ensure output changes only once per clock cycle Ensure output changes only once per clock cycle  Two commonly-used types of flip-flops: Master-Slave Master-Slave  Use a sequence of two latches Edge-Triggered Edge-Triggered  Implementation very different from latches

17 1. Master-Slave Flip-Flop  Either Master or Slave is enabled, not both

18 Timing Diagram  Trace the behavior  Note illegal state  Is it transparent?

19 Have We Fixed the Problem?  Output no longer transparent Combinational circuit can use last values Combinational circuit can use last values New inputs appear at latches New inputs appear at latches Not sent to output until clock low Not sent to output until clock low  But changes at input of FF when clock high do trigger next state Is this a problem? Is this a problem?  As clock faster, more problems  Have to guarantee circuit settles while clock low

20 2. Edge-Triggered Flip-Flops  New state latched on clock transition Low-to-high or high-to-low Low-to-high or high-to-low  +ve edge-triggered, -ve edge-triggered  Also: dual-edge-triggered Changes when clock high are ignored Changes when clock high are ignored  Note: Master-Slave sometimes called pulse triggered

21 D-Type Edge-Triggered  Is this +ve or –ve edge-triggered?

22 Standard Symbols – Latches  Circle at input indicates negation

23 Symbols – Master-Slave  Inverted ‘L’ indicates postponed output  Circle indicates whether enable is positive or negative  JK: like an SR flip-flop, but: If J=K=1, output is toggled If J=K=1, output is toggled Can make a toggle flip-flop (T flip-flop) from a JK Can make a toggle flip-flop (T flip-flop) from a JK

24 Symbols – Edge-Triggered  Arrow indicates edge trigger

25 Direct Inputs  Use to force Set/Reset independent of clock Direct set or preset Direct set or preset Direct reset or clear Direct reset or clear  Often used for power-up reset

26 Flip-Flop Timing  Setup time – time that D must be steady before clock edge  Hold time – time that D must continue to be steady after clock edge

27 Propagation Delay  Propagation delay – time after edge until output becomes available

28 Clock Pulse Requirements  Determine the max clock frequency

29 In Passing: Clock Gating and Skew  Can ‘gate’ or freeze clocks …to keep any FF from changing states …to keep any FF from changing states Can help reduce power consumption Can help reduce power consumption  However, can cause clock skew Clock edges at different times on different FFs Clock edges at different times on different FFs  Clock skew also caused by wire lengths over chip

30 Next Time  State Diagrams Sec. 6-4 and 6-5 Sec. 6-4 and 6-5 Pages Pages Skip last part of 6-5 Skip last part of 6-5  Verilog to describe state machines