© BYU 11b MSFF Page 1 ECEn 224 MSFF Master/Slave Flip Flops

© BYU 11b MSFF Page 2 ECEn 224 A Master/Slave Flip Flop (D Type) Gated D latch (master)Gated D latch (slave) D Q Gate D Q Gate D GATE Q Q1 Either: The master is loading (the master in on) or The slave is loading (the slave is on) But never both at the same time…

© BYU 11b MSFF Page 3 ECEn 224 DFF Timing Gate D Q1 Q Master Loads Slave Loads time D Q Gate D Q Gate D GATE Q Q1

© BYU 11b MSFF Page 4 ECEn 224 Output Changes in Response to Falling Clock Gate D Q1 Q Master Loads Slave Loads time D Q Gate D Q Gate D GATE Q Q1

© BYU 11b MSFF Page 5 ECEn 224 DFF Detailed Schematic D CLK Q Q’ Master latch (D)Slave latch (SR) Usually call the gate “clock”

© BYU 11b MSFF Page 6 ECEn 224 A Falling Edge Triggered DFF D CLK Q Q’ CLK D Q Edge-triggered Falling edge triggered

© BYU 11b MSFF Page 7 ECEn 224 Oscillator (Toggle Circuit) Operation Q CLK time QD D Q

© BYU 11b MSFF Page 8 ECEn 224 Rising Edge Triggered DFF Schematic D CLK Q Q’ D Q CLK Edge-triggered Rising edge triggered

© BYU 11b MSFF Page 9 ECEn 224 Oscillator (Toggle Circuit) Operation Q CLK time CLK QD D Q

© BYU 11b MSFF Page 10 ECEn 224 D Flip Flop Transition Table Q+ = D No clock shown since it is edge triggered (assumed)

© BYU 11b MSFF Page 11 ECEn 224 Falling vs. Rising Edge Triggered D Q D CLK Q fall CLK Q rise CLK D Q rise Q fall

© BYU 11b MSFF Page 12 ECEn 224 Alternative Flip Flops T JK

© BYU 11b MSFF Page 13 ECEn 224 Toggle Flip Flop T Q CLK QT Q+ = T’Q + TQ’ = T + Q Clock edge is assumed in this transition table…

© BYU 11b MSFF Page 14 ECEn 224 Toggle Flip Flop T Q CLK QT Q+ = T’Q + TQ’ = T + Q D Q T Q CLK An oscillator with an enable input (T)

© BYU 11b MSFF Page 15 ECEn 224 Toggle Flip Flop Q T CLK

© BYU 11b MSFF Page 16 ECEn 224 JK Flip Flop J Q K CLK QJ K Q+ = K’Q + JQ’ Kind of a cross between a SR FF and a T FF

© BYU 11b MSFF Page 17 ECEn 224 JK Flip Flop Q J CLK K

© BYU 11b MSFF Page 18 ECEn 224 Why Alternative FF’s? With discrete parts (TTL family) –JK or T FF’s could reduce gate count for the input forming logic –Extensively used With VLSI IC’s and FPGA’s –JK or T FF’s must be built from DFF+gates –Larger, slower than a DFF –Not used

© BYU 11b MSFF Page 19 ECEn 224 Flip Flops With Additional Control Inputs

© BYU 11b MSFF Page 20 ECEn 224 D CLK Q Q’ What is this? ???

© BYU 11b MSFF Page 21 ECEn 224 CLK What is this? Enable A falling edge triggered, D-type FF with enable Master only loads when CLK = Enable = 1 D Q Q’

© BYU 11b MSFF Page 22 ECEn 224 CLK What is this? ??? D Q Q’

© BYU 11b MSFF Page 23 ECEn 224 CLK What is this? Set A falling edge triggered, D-type FF with an asynchronous set If Set=1 then Q → 1, regardless of CLK or D D Q Q’

© BYU 11b MSFF Page 24 ECEn 224 CLK What is this? ??? D Q Q’

© BYU 11b MSFF Page 25 ECEn 224 CLK What is this? A falling edge triggered, D-type FF with a synchronous set If Set=1 then Q → 1 on the next falling edge of the clock, regardless of D Set D Q Q’

© BYU 11b MSFF Page 26 ECEn 224 Flip Flops With Additional Control Inputs A variety of FF’s have been made over the years They contain combinations of these inputs: –Enable/load –Set –Reset/clear The Set and Reset can be either: –Asynchronous (independent of CLK) –Synchronous (work only on CLK edge)

© BYU 11b MSFF Page 27 ECEn 224 Flip Flop Timing Characteristics

© BYU 11b MSFF Page 28 ECEn 224 Clock-to-Q Time ( t CLK  Q ) CLK t CLK  Q = t NOT + t AND + 2 x t NOR The output does not change instantaneously… D Q Q’

© BYU 11b MSFF Page 29 ECEn 224 t CLK  Q CLK D Q t CLK  Q time

© BYU 11b MSFF Page 30 ECEn 224 Setup Time ( t setup ) D CLK Q Q’ t setup = t NOT + t AND + 2 x t NOR The input has to get there early enough to set the master latch before the clock turns off…

© BYU 11b MSFF Page 31 ECEn 224 t setup CLK D Q t setup time

© BYU 11b MSFF Page 32 ECEn 224 Setup Time ( t setup ) D CLK Q Q’ Same setup time as before

© BYU 11b MSFF Page 33 ECEn 224 Setup Time ( t setup ) D CLK Q Q’ Clock is delayed through the NOT gate

© BYU 11b MSFF Page 34 ECEn 224 CLK Q Time CLK inv D t setup-old t not Rising Edge FF Setup Time (t SETUP ) Falling-edge setup time

© BYU 11b MSFF Page 35 ECEn 224 CLK Q Time CLK inv D t setup-old t not t setup Rising Edge FF Setup Time (t SETUP )

© BYU 11b MSFF Page 36 ECEn 224 Falling Edge Hold Time ( t hold ) D CLK Q Q’ t hold = 0ns (AND gates turn off immediately) You have to keep the old D value there until the AND gates are shut off… (but no longer)

© BYU 11b MSFF Page 37 ECEn 224 Rising Edge Hold Time ( t hold ) D CLK Q Q’ t hold = t NOT You have to keep the old D value there until the AND gates are shut off…

© BYU 11b MSFF Page 38 ECEn 224 Rising Edge Hold Time ( t hold ) CLK D Q t hold = t NOT time Clock edgeAND gate turns off, D can now change

© BYU 11b MSFF Page 39 ECEn 224 Flip Flop Timing CLK D Q t setup t hold t CLK  Q time

© BYU 11b MSFF Page 40 ECEn 224 Timing of a Synchronous System CLK D Q CLK D Q Input Forming Logic Input Forming Logic time QD CLK Q D t CLK  Q t IFL t SETUP t CYCLE >= t CLK  Q + t IFL + t SETUP

© BYU 11b MSFF Page 41 ECEn 224 D Q Example of a Synchronous System D Q +1 Circuit 4 CLK 44 CNT = … … One transition per clock edge…