Digital System Projects

Behavioral Description Design Environment Design => Compile => Simulate Our first VHDL code Reading: –Bhasker Ch 1, 3.1, 3.2, 3.3 (data objects) –ECE200 Textbook on Adder

Design Environment File system Project file structure –Folder (directory) for the whole project –Subdirectories Source code directory Work directory

Our 1 st VHDL Code library ieee; use ieee.std_logic_1164.all; entity full_adder is port (A, B, CIN : in std_logic; COUT, SUM : out std_logic); end full_adder; architecture behav of full_adder is begin process(A, B, CIN) begin SUM <= A xor B xor CIN; COUT <= (A and B) or (B and CIN) or (CIN and A); end process; end behav;

VHDL Features IEEE library and std_logic_1164 package Entity –Port –data type std_logic for signals Architecture –Declaration –Body Process statement –Software description –Sensitivity list: signals whose events trigger code execution –Execution suspends all internal signals updated

3-bit Adder Example Architecture behav2 of full_adder is begin process(a, b cin) variable count : integer; begin count := 0; -- count number of one’s if a='1' then count := count + 1; end if; if b='1' then count := count + 1; end if; if cin='1' then count := count + 1; end if; -- now convert count to zero's ones if count = 0 then cout <= '0'; sum <= '0'; elsif count = 1 then cout <= '0'; sum <= '1'; elsif count = 2 then cout <= '1'; sum <= '0'; elsif count = 3 then cout <= '1'; sum <= '1'; end if; end process; end behav2;