Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C Chapter 8 – Machine Instructions These are lecture notes to accompany the book SPARC Architecture, Assembly Language Programming, and C, by Richard P. Paul, 2 nd edition, Updated Spring 2014

Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C Decoding Instructions SPARC Instructions are 32 bits long Bits specify the “op” field These first 2 bits indicate how the other bits should be handled. op

Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C Decoding Instructions Instructions are classified according to “op” op opInstruction class 00Branch instructions 01 Call instructions 10Format Three instructions 11Format Three instructions

Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C Format 1 Instructions Call instruction The displacement must be word aligned Address is calculated by right shifting displacement 2 positions 0130 bit displacement

Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C Format 2 Instructions branch 0 0 a cond op2 22 bit immediate sethi 0 0 rd bit immediate

Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C Branch Instructions The branch is (or is not) taken based on the “cond” (condition) field. op2 = 010 means integer condition code condbranch type 1000always 1001if not equal to zero 1010if greater than zero 1011if greater than or equal to zero 1100if greater, unsigned 1101if carry is clear 1110if positive 1111if overflow is clear condbranch type 0000never 0001if equal to zero 0010if less than or equal to zero 0011if less than zero 0100if less or equal, unsigned 0101if carry set 0110if negative 0111if overflow is set

Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C Format 3 Instructions 2 source registers 1 x rd op3 rs1 0 rs Immediate constant 1 x rd op3 rs1 1 signed 13-bit #

Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C Format Three Instructions Not all possible bits patterns are used op = 10 op3Instruction add and or xor sub andn orn xnor addx op3Instruction jumpl rett ticc iflush save restore See page 235 for a complete list

Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C Format Three Instructions Not all possible bits patterns are used op = 11 op3Instruction ld ldub lduh ldd st stb sth std See page 236 for a complete list

Register coding RegisterSynonyms %g0%r0 %g1%r1 %g2%r2 %g3%r3 %g4%r4 %g5%5 %g6%r6 %g7%r7 Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C RegisterSynonyms %o0%r8 %o1%r9 %o2%r10 %o3%r11 %o4%r12 %o5%r13 %o6%r14 %o7%r15 RegisterSynonyms %l0%r16 %l1%r17 %l2%r18 %l3%r19 %l4%r20 %l5%r21 %l6%r22 %l7%r23 RegisterSynonyms %i0%r24 %i1%r25 %i2%r26 %i3%r27 %i4%r28 %i5%r29 %i6%r30 %i7%r31

Load/Store instructions Load and Store instructions have two references – a register and memory location rd field – refers to the register component rs1 field – refers to register for memory address rs2 field/immediate – refers to offset for memory address Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C

Load/Store examples ldub [%o3 + %l2], %o1 stb %l0, [%o1 + %o2] stb %o5, [%o1 + 50] Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C rd rs1 rs2 immediate rs1 rs2 rd

Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C Example Decode the following commands: save %sp, -96, %sp ld [%fp-20], %o0 mov 4, %o1 add %o0, %o1, %o0 st %o0, [%fp-20] ret restore 0x9de3bfa0 0xd007bfec 0x x xd027bfec 0x81c7e008 0x81e80000