Low-Power BIST (Built-In Self Test) Overview 10/31/2014 Harsh N. Patel

Motivation ⇒ Leads to energy constraint design Source: herculsecyborg.blogspot.com The key challenges for SRAM include VCCMIN, leakage and dynamic power reduction while relentlessly following Moore’s law to shrink the area by 1/2— for every technology generation. As the transistor feature size marches toward sub-30nm, device variation has made it very difficult to shrink the bit cell size at the 2× rate while maintaining or lowering VCCMIN between generations. Starting at 45nm, the introduction of high-k metal-gate technology reduces the Vt mismatch and enables further device scaling by significantly reducing the equivalent oxide thickness. Starting at 22nm and beyond, new transistors such as FinFETs and fully-depleted SOI are key to enabling the continuous scaling of bit cell area and low voltage performance. Design solutions such as read/write assist circuitry have been used to improve SRAM VCCMIN performance starting at 32nm. New SRAM bit cells with more than 6 transistors have also been proposed to minimize operating voltage. For example, 8T register file cells have been reported in recent products requiring low VCCMIN. Dual-rail SRAM design emerges as an effective solution to enable dynamic voltage-frequency scaling (DVFS) by decoupling logic supply rails from SRAM arrays and thus allowing much wider operating window. It is important for SRAM to reduce both leakage and dynamic power, keeping products within the same power envelope at the next technology node. Sleep transistors, fine-grain clock gating and clock-less SRAM designs have been proposed to reduce leakage and dynamic power. ⇒ Leads to energy constraint design

Motivation Sub-threshold region Source: N. Verma, IEEE TED 2008 Energy is divided in Active and Leakage and the optimal point stays in sub-Vt region. Source: N. Verma, IEEE TED 2008

Motivation Source: M.H. Abu-Rahma, Springer 2013 ⇒ Higher occupancy of the memory leads higher energy dissipation at SoC level ⇒ SRAM required to be operated in the sub-threshold region for energy constrained design.

Motivation But lowering supply voltage leads to cell write failures. ⇒ Failures at lower supply necessitate the requirement of some kind of assist technique to “help” SRAM cell in writing in to it.

Outline SRAM overview Write Assist Techniques Conventional SRAM cell Write Operation Write Assist Techniques Choice of Evaluation Metrics Results Conclusion

SRAM: Overview Static Random Access Memory Data stored on cross-coupled inverters and being accessed by pass transistors. Data storage is Static in nature, i.e. nodes are connected to VDD/GND through PMOS/NMOS as switch.

SRAM: Overview Conventional 6 Transistors Cell

SRAM Cell- Write Operation Performing write-0 operation to the cell holding ‘1’ Write 0 Operation for a 6T cell holding ‘1’

Write-Assist Techniques Performing write-0 operation to the cell holding ‘1’ Write Assist: Theory 𝑰 𝑫 ∝ 𝑾 𝑳 𝒆 𝑽 𝑮𝑺 𝒏 𝑽 𝒕𝒉𝒆𝒓𝒎𝒂𝒍 Weakening the PMOS: VDD Lower (↓ VS) VSS Raise (↑ VG) Strengthening the NMOS: WL Boosting (↑ VG) Negative BL (↓ VS)

Write Assist Techniques a) VDD Lowering b) VSS Raising c) WL Boosting d) Negative Bitline

Choice of Assist Evaluation Metrics Dynamic (time dependent ) - Static (time independent ) write ability: Dynamic Write-Ability : The time by which write operation should be completed; speed of the operation is main concern. Critical wordline pulse (WLcrit): minimum width of word-line(WL) pulse during which the bitcell changes state. < WLcrit ≥ WLcrit Source: [1]

Choice of Assist Evaluation Metrics Dynamic (time dependent ) - Static (time independent ) write ability: Static Write-Ability (Write Margin): The speed of operation is not prime goal; but the functionality at possible lower supply n1 n2 VDD WL Sweep Write Margin (WM) For the energy constrained application space where the device operating voltage is below the threshold voltage of the device, therefore operating speed is no longer the main constraint, but the functionality. For this reason, the metric for assist evaluation is to be decided based on the SRAM usage in the application. With the WM as the static metric, the effect of each assists on timing is captured with write delay. “An ability of the cell to get flipped before the word line voltage reaches to the maximum voltage of WL signal”

Results: Test Setup Tool : Technology Agnostic Simulation Environment (TASE) Technology : commercial 130nm node. Tests : Write Margin Measurement : Apply assist with step of 10-20-30% of supply. e.g. for VDD=0.5V 10% VDD Lowering  VDD = 0.45V 10% VSS raising  VSS = 0.05V 10% WL Boosting  WL = 0.55V 10% NegBL  BL(holding 0) = -0.05V

WL Boosting brings Vmin down to VDD=0.3V Results: Write Margin WL Boosting brings Vmin down to VDD=0.3V Min. possible operating supply voltage(Vmin) Vmin reduced to 0.5V from 0.7V Write Margin across supply: Without Assist Supply Voltage (V) Take away Points: WL Boosting is the optimal assist technique to scale the supply down to VDD=0.3V WL Boosting increases Write Margin by ~7X across the supply voltages.

Conclusion Metric for evaluation vary based on application of device. Assist techniques help to reduce Vmin for SRAM. Vmin can be reduced to VDD=0.3V using 30% of WL boosting WL boosting improves WM across the supply voltages by ~7X.

References V. Chandra, R. Aitken, C. Pietrzyk, “On the Efficacy of Write Assist Techniques in Low Voltage Nanoscale SRAMs”, DATE, 2010. R. W. Mann, J. Wang, S. Nalam, S. Khanna, G. Braceras, H. Pilo and B.H. Calhoun, “Impact of circuit assist methods on margin and performance in 6T SRAM” Solid State Electron., Nov 2010. B. Calhoun, A. Wang, A. Chandrakasan, “Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuit. JSSC, 2005. Verma, N.; Chandrakasan, A.P., “A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy” IEEE Journal of Solid-State Circuits, JSSC 2007. Boley, James ; Chandra, Vikas ; Aitken, Robert ; Calhoun, Benton, “Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013

Thank You! Questions?

Backup ION/IOFF Improvement

Backup Points with WM > 150mV and Write Delay < 2