Custom DDS Board Design By Weizhi Chua

Motivations Exercise knowledge learned from class in a design project. Customer: Lei Shi Current radar system is implemented without DDS Make custom DDS board for more quality in waveform generation.

Hardware Goals & Specs Compact board Waveform generation in the range of 2.4 GHz to 2.5 GHz. To be used in conjunction with FPGA eval board. Can migrate waveform generator section and FPGA and other components of the radar in the future.

Hardware Goals & Specs Cable: i.e: ribbon cable Chirp wave DDS board GPIO header De0 Nano Cyclone IV Eval Board

How do DDS work? Output waveform limited by sampling speed of DAC Phase accumulator DAC N- bit Sine Look Up Table Output waveform limited by sampling speed of DAC Look Up Table stores amplitudes of a single cycle of Sine Wave Phase accumulator addresses the look up table Low frequencies, small increments in phase accumulator, and opposite for high frequencies.

Components of the DDS Hardware Reconstruction Filter IF Xtal RF OUT Amplification and Conditioning VCO LO

Components of the DDS Hardware AD9954 DDS (400 Msps DAC ~ max 200MHz output) 25 MHz Crystal 2.3 GHz to 2.5 GHz VCO Mixer Filters and Op Amp

AD9954 3 1 2

AD9954 Programming Via SPI ports Ports: SCLK, !CS, SDIO, SDO, IO_UPDATE, SYNC_CLK However: SCLK, SDIO and IO_UPDATE needed. !CS tied LOW. IO_UPDATE to complete programming.

AD9954 Chirp Operation Rising PS0 signal to trigger sweeping. PS0 synchronous to SYNC CLK.

Interface with FPGA High Speed (HS) Signals: SCLK, SDIO, PS0, SYNC_CLK Low Speed (LS) Signals: IO_UPDATE, RESET. Strategy: Separate Header Connectors between HS and LS far apart. GND connection for every HS signal

To Dos Schematic and Layout (focus on DDS) Board stack up considerations Trace widths considerations Termination considerations Trace length considerations Power and Thermal Analysis for DDS