November 29, 2011 Final Presentation

Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing Michael McCoy Computer Engineer Microblaze Programmer Cooper McClain Computer Engineer Top Level Development Nicholas Robinson Computer Engineer Top Level Development

Outline Background Problem Solution System Overview Constraints o Technical o Practical Design Decisions Testing State of Project Current Plans

Background G.729 protocol provides a highly intelligible voice codec with low bandwidth requirements. NASA is currently searching for a hardware based (FPGA) alternative to their current DSP-based G.729 system.

Problem - Power Consumption Mathematical complexity of G.729 algorithm CPU system requires multiple clock cycles per instruction High frequency CPU requirements in order to meet timing goals More clock cycles = more power

Solution - ITU G.729 FPGA Encoder FPGA implementation of ITU G.729 Encoder Algorithm Multiple math functions in a single clock cycle Reduction in frequency

System Overview

NameDescription TimeThe encoder must completely process a single frame in less than 10 ms. PowerThe encoder must consume less than 1.8W during activity. InputThe encoder must be able to interpret three 80x16-bit frames of sampled input OutputThe output of the FGPA encoder must provide a bit-exact representation of the ITU C model. SizeThe synthesized project must fit onto one Xilinx Virtex-5 FPGA Technical Constraints

Practical Constraints CategoryNameDescription SustainabilityReadabilityThe RTL code must be structured around a set of linting rules. SustainabilityModularityThe encoder must be modular in design for maintenance and optimization

Readability Code must be structured around linting rules Linting Rules: o Proper formatting of white space o Line length o Indentations o Bracing styles Why is this important?

Modularity Maintenance o System debugging can be done on smaller amounts of code o Allows for simple integration into top level Distribution o Different modules can be assigned to individual group members

Design Modifications New Top Level Testbench o Originally only tested the newest integrated submodule o Regressively test all integrated submodules Extension of the memory o Originally 11 bits (2048 locations) o Now 12 bits (4096 locations)

Top Level Testing Verify the output of the Top Level Behavioral simulation is very fast but does not consider timing delays Need to be able to verify timing for constraint purposes

Current State of Project RTL gives correct output for 100+ iterations Issues o Timing issues showing up in reports o Issues with clocking the encoder Microblaze to Encoder Interface

RTL Progress Encoder is fully integrated 100+ iterations of Encoder gives correct output out of 128 Encoder has errors beyond this point to be fixed

Timing Issues The target frequency of 50 MHz has not been met Analysis of critical paths within the design is being done to eliminate timing delays and achieve the target frequency Isolation of sub modules in the top level is the current approach with the anticipation of eliminating false paths

Microblaze Encoder Interface Progress Test Interface o Tests that the Interface module can send and receive data to an instantiated module Clocking the Encoder o Figure out what speed the complete encoder will run at by adjusting the clock of the microblaze Finishing the Encoder o Instantiate smaller pieces of the encoder and run them on the board to verify their output

Size Verification Total Slice LUTs: 69,120 Approximately 76% of the board G.729: 43,157 LUTs Microblaze: 9,752 LUTs

Current Plan Finish debugging of top level Identify critical paths by running synthesis on smaller segments of encoder Find frequency at which encoder runs on FPGA

References [1] T.Morris, “Field Programable Gate Array (FPGA) Based Speech Encoding,” unpublished [2] ITU. (2007, January). ITU-T Recommendation of G.729 [Online].Available: =e&id=T-REC-G I!!SOFT-ZST-E&type=items

Questions?