CE 478: Microcontroller Systems University of Wisconsin-Eau Claire Dan Ernst The Pentium Pro® (P6) Bus Reference: “Penium Pro and Pentium II System Architecture”

CE 478: Microcontroller Systems University of Wisconsin-Eau Claire Dan Ernst A Bus for a Different Purpose Context: –The “P6” architecture was originally used in the “Pentium Pro” line, which was targeted at high-performance and SMP (Symmetric MultiProcessing) users. –The P5 (Pentium) bus was very simple One thing at a time - max Among other things, had very poor support for multiprocessing –Intel decided to redesign the bus interface to natively support: More complicated transactions for higher performance Basic cache coherence signals for multiprocessor efficiency

CE 478: Microcontroller Systems University of Wisconsin-Eau Claire Dan Ernst 3 Types of “Agents” on the bus –Request Agents –Response Agents – Snooping Agents

CE 478: Microcontroller Systems University of Wisconsin-Eau Claire Dan Ernst Who can do what? Examples of each type: Request Agents –CPU(s) –PCI or other bridge or I/O agents Response Agents –Memory Controller –PCI or other bridge or I/O agents Snooping Agents –CPU(s) –Stand-alone bus-attached caches

CE 478: Microcontroller Systems University of Wisconsin-Eau Claire Dan Ernst Phases The P6 bus divides each transaction into 6 phases –Arbitration –Request –Error –Snoop –Response –Data Each phase uses a different (mutually exclusive) set of signals on the bus –Key issue: why?

CE 478: Microcontroller Systems University of Wisconsin-Eau Claire Dan Ernst CS 352 Flashback In our basic processor, each instruction had 5 “steps” it had to work through: –Fetch, Decode, Execute, Memory, Write-back Single-cycle and multi-cycle designs dictated : –No new instruction can start until the previous instruction is completely finished. Architects used pipelining to greatly increase throughput of the machine –When an instruction leaves a stage, another can use those resources add$t4, $t5, $t6 FDEMW beq$t1, $t2, loop FDEMW lw$t3, 300($zero) FDEMW

CE 478: Microcontroller Systems University of Wisconsin-Eau Claire Dan Ernst Bus Pipelining We can accomplish the same goal (increased throughput) on busses –Substitute “Transaction” for “Instruction” Allow multiple transactions to be in-flight at once –Each in a different “step” (phase) of the transaction Key requirement – physical resources ( i.e. bus lines) cannot be shared among phases –Just like hardware could not be shared between processor pipeline stages

CE 478: Microcontroller Systems University of Wisconsin-Eau Claire Dan Ernst Step-by-Step – Part I – Arbitration The P6 bus uses symmetric arbitration, meaning that all request agents on the bus decide amongst themselves who is granted the bus next. –Recall PowerPC uses a central bus arbiter – the P6 bus has no arbiter. Who gets to go in the case of a conflict? –The bus uses a rotational priority scheme –Each agent keeps track of who has the bus and who is next in line –Exception: a denoted priority agent can trump the rotational scheme

CE 478: Microcontroller Systems University of Wisconsin-Eau Claire Dan Ernst Step-by-Step – Part 2 – Request Once you have successfully taken control of the bus, you can make a request (provided someone else isn’t already) Request phase lasts 2 cycles –2 “packets” of data are transferred across the request lines

CE 478: Microcontroller Systems University of Wisconsin-Eau Claire Dan Ernst Step-by-Step – Part 3 – Error Pretty Simple: if the request’s parity failed at the receiver end, an error signal (AERR#) is asserted, and the transaction needs to start over.

CE 478: Microcontroller Systems University of Wisconsin-Eau Claire Dan Ernst Step-by-Step – Part 4 – Snoop If another (snoop) agent on the bus is holding a more up-to-date copy of a certain piece of data, it gets a chance to intervene. –This is necessary to support “cache coherence” (CE 452) If a snooper wants to interfere, its signal will dictate how the next 2 phases develop. This is also the phase where a response agent can opt to DEFER

CE 478: Microcontroller Systems University of Wisconsin-Eau Claire Dan Ernst Step-by-Step – Part 5 – Response Response agent will give its official response. This can include: –Retry/Defer –No Data –Normal Data –Hard Failure Sets us up for…

CE 478: Microcontroller Systems University of Wisconsin-Eau Claire Dan Ernst Step-by-Step – Part 6 – Data The Data is transferred over the data bus (64-bit) Who does the transferring depends on: –Request type (R/W) –Response type –Snoop results