COE 308: Computer Architecture (T032) Dr. Marwan Abu-Amara Integer & Floating-Point Arithmetic (Appendix A, Computer Architecture: A Quantitative Approach,

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Appendix J Authors: John Hennessy & David Patterson.
Presentation transcript:

COE 308: Computer Architecture (T032) Dr. Marwan Abu-Amara Integer & Floating-Point Arithmetic (Appendix A, Computer Architecture: A Quantitative Approach, J. Hennessy & D. Patterson, 1 st Edition, 1990)

Monday, March 29, 2004 COE 308 (T032) – Dr. Marwan Abu-Amara 2 Basic Techniques of Integer Arithmetic Ripple-Carry Addition:  Half Adder: Takes 2 inputs a i & b i and produces a sum bit, s i, and a carry bit, c i+1, as output Mathematicallys i = (a i + b i ) mod 2 c i+1 =  (a i + b i ) / 2  Logically c i+1 = a i b i

Monday, March 29, 2004 COE 308 (T032) – Dr. Marwan Abu-Amara 3 Basic Techniques of Integer Arithmetic (cont.) Ripple-Carry Addition:  Full Adder: Takes 3 inputs a i, b i, & c i and produces a sum bit, s i, and a carry bit, c i+1, as output Logically c i+1 = a i b i + a i c i + b i c i  Problem in building an n-bit adder is propagating the carries  Ripple-carry adder uses n full adders to build an n-bit adder  Delay of c i+1 is 2 levels of logic  2n logic levels in an n-bit adder (i.e. O(n) to generate final result)  Can use n-bit adder to get A–B by feeding A into “A” input & inverse of B into “B” input, and set c 0 to 1

Monday, March 29, 2004 COE 308 (T032) – Dr. Marwan Abu-Amara 4 Basic Techniques of Integer Arithmetic (cont.)

Monday, March 29, 2004 COE 308 (T032) – Dr. Marwan Abu-Amara 5 Radix-2 Multiplication & Division Multiplication: 2 unsigned numbers, A & B (a n-1 a n-2 … a 1 a 0 & b n-1 b n-2 … b 1 b 0 ). Register P (i.e. product) is initially set to 0. Algorithm: Repeat n times 1. If least significant bit of A is 1  P = P + B Otherwise  P = P Shift the register pair P & A to right by 1 bit such that low- order bit of P is moved into A’s high-order bit, and low-order bit of A is shifted out  Final result is in the register pair P & A with P having the high order bits

Monday, March 29, 2004 COE 308 (T032) – Dr. Marwan Abu-Amara 6 Radix-2 Multiplication & Division “Restoring” Division: 2 unsigned numbers, A & B (a n-1 a n-2 … a 1 a 0 & b n-1 b n-2 … b 1 b 0 ). Register P is initially set to 0. Algorithm: Repeat n times 1. Shift register pair P & A one bit left (with high-order bit of A moved into P’s low-order bit) 2. Subtract B from P (i.e. P = P – B) 3. If result of step 2 < 0 (i.e. (–)ve)  Set low-order bit of A to 0 Otherwise  Set low-order bit of A to 1 4. If result of step 2 < 0 (i.e. (–)ve)  P = P + B  Final result: A = quotient, P = remainder

Monday, March 29, 2004 COE 308 (T032) – Dr. Marwan Abu-Amara 7 Radix-2 Multiplication & Division

Monday, March 29, 2004 COE 308 (T032) – Dr. Marwan Abu-Amara 8 Example of Division Divide 14 by 3  A = 14 = & B = 3 = Iteration Step P A Iteration Step P A. Initial _ _ (add B to P) (add B to P) _  Quotient = A = = Remainder = P = _ = (add B to P)

Monday, March 29, 2004 COE 308 (T032) – Dr. Marwan Abu-Amara 9 Radix-2 Multiplication & Division Non-Restoring Division: 2 unsigned numbers, A & B (a n-1 a n-2 … a 1 a 0 & b n-1 b n-2 … b 1 b 0 ). Register P is initially set to 0. Algorithm: Repeat n times If P is (–)ve: 1. Shift register pair P & A one bit left 2. P = P + B Else (i.e. If P is not (–)ve): 1. Shift register pair P & A one bit left 2. P = P – B If P is (–)ve  Set low-order bit of A to 0 Otherwise  Set low-order bit of A to 1  Final result: A = quotient, P = remainder

Monday, March 29, 2004 COE 308 (T032) – Dr. Marwan Abu-Amara 10 Signed Numbers 4 methods: 1. Sign magnitude 2. 1’s complement 3. 2’s complement(most widely used) 4. Biased: A fixed bias is picked so that sum of bias & # represented is always > 0 (used in floating-point) Example: Represent –3 in (1) sign magnitude, (2) 1’s complement, (3) 2’s complement 3 =  (1) sign magnitude: – =  (2) 1’s complement:  (3) 2’s complement:1101 2

Monday, March 29, 2004 COE 308 (T032) – Dr. Marwan Abu-Amara 11 Signed Numbers (cont.) Overflow in unsigned #s: when there’s a carry-out of MSB Overflow in 2’s complement: when carry-in to MSB is different from carry-out of MSB Example: –5 + (–7)  10  different 1011(–5)  overflow (–7) (–7)  00  same 0101(+5)  no overflow (–7) 1110