09/01/2016James Leaver SLINK Current Progress

09/01/2016James Leaver Hardware Setup Slink Receiver Generic PCI Card Slink Transmitter Transition Card (ECAL) VME Backplane FED Controller Slink Controller Control via VXI-MXI-2 LVDS Cable FED

09/01/2016James Leaver Slink Verification Configure FED to send test patterns: –Simple counter –Alternate lines of all As and all 5s Drive FED with software triggers: –Throttle triggers using software ‘waits’ and by setting QDR buffer occupancy thresholds Simply receives all data sent from FED Compares received data with current expected test pattern FED PCSLINK PC

09/01/2016James Leaver Green Green: Slink CLK Yellow Yellow: Write Enable Blue Blue: Bit 0 of Data Stream Pink Pink: Bit 1 of Data Stream Example Data Transmission Test Pattern: Alternate lines of As and 5s, Scope Length: 10 Measured from Transition Card

09/01/2016James Leaver Green Green: Slink CLK Yellow Yellow: Write Enable Blue Blue: Bit 0 of Data Stream Pink Pink: Bit 1 of Data Stream A Bad Clock? Test Pattern: Alternate lines of As and 5s, Scope Length: 10 Measured from Transition Card, Persistent Display

09/01/2016James Leaver Green Green: Slink CLK Yellow Yellow: Write Enable Blue Blue: Bit 0 of Data Stream Pink Pink: Bit 1 of Data Stream Clock Signal at the FED Measured on the FED; Slink Connected

09/01/2016James Leaver Green Green: Slink CLK Yellow Yellow: Write Enable Blue Blue: Bit 0 of Data Stream Pink Pink: Bit 1 of Data Stream Clock Signal at the FED Measured on the FED; Transition Card Disconnected

09/01/2016James Leaver Spice Model of Clock Path

09/01/2016James Leaver Spice Model Results Blue Blue: CLK at FED VME connector Red Red: CLK at output connector on Transition Card Yellow Yellow: CLK at input to Transmitter FPGA

09/01/2016James Leaver The Only Way to Remove Reflections…?

09/01/2016James Leaver The Only Way to Remove Reflections…? CLK is good at all locations – but impractical hardware solution

09/01/2016James Leaver Clock at Input to Transmitter FPGA The Slink clock is clean where it matters, as Spice model predicts

09/01/2016James Leaver Slink Error Rates Have sent 18.3 Gbytes of data from FED to Slink Receiver –Used alternate lines of all As and all 5s; highest possible switching rate No errors observed in transmitted data  Probability that a word will be transmitted incorrectly via Slink is: 1.22 x 10 95% CL

09/01/2016James Leaver Required Data Rates To guarantee (95% CL) that no more than 1 word will be sent incorrectly per month of normal LHC operation, need to transmit words (without errors) At current maximum data rate, would take ~16 years! Need to find a way to increase data rate: –Could potentially output ~600 Mbytes/sec from the FED (reducing validation time to ~30 days)

09/01/2016James Leaver FED Behaviour at High Data Rates With a fixed wait of > 60.07ms between software triggers: –QDR buffer always empty when next trigger arrives –FED operates normally With a fixed wait of < 60.07ms between software triggers: –QDR buffer rapidly fills to current limit (1→ 10 frames) –FED operates normally for some period of time –FED randomly stops sending data An Extreme Example Test Pattern: Alternate lines of all As and all 5s, Scope Length: 1020

09/01/2016James Leaver Why Does the FED Stop? Backpressure from the Slink? –At high trigger rates, backpressure is exerted multiple times during period in which FED is working Overflow of QDR Buffer? –FED stops working even with a QDR buffer limit of 1 frame Overflow of Front End Buffer? –Backend Status Register would indicate not… –But getChannelBufferOccupancy() function in ‘Fed9U’ software returns dubious values –Seems most likely cause

09/01/2016James Leaver Data Rate Challenges Need to prevent FED lock-ups Software triggers insufficient –Limited to a maximum of ~100 Hz –Need to use hardware triggers - generated with FED Tester? Need to increase efficiency with which Slink PC manages received data –Currently have to run Slink software in ‘debug’ mode (raw data access) due to mismatch between output FED header/trailer words and format required for automatic event handling

09/01/2016James Leaver Conclusion Data can be read from the FED via Slink No errors yet observed Nothing to suggest that FED hardware requires modification Firmware/Data Rate issues to be resolved…