PCI B ASED R EAD-OUT R ECEIVER C ARD IN THE ALICE DAQ S YSTEM W.Carena 1, P.Csato 2, E.Denes 2, R.Divia 1, K.Schossmaier 1, C. Soos 1, J.Sulyan 2, A.Vascotto 1, P.Vande Vyvre 1 1 CERN EP/AID, 2 KFKI-RMKI (Budapest) NEC 2001 Varna, Bulgaria 12 – 18 September, 2001

PCI based read-out receiver cardNEC2001, September, O UTLINE  ALICE DAQ system  DDL components  DDL requirements  PCI-RORC concept  PCI-RORC development  PCI-RORC performance  Summary

PCI based read-out receiver cardNEC2001, September, ALICE DAQ S YSTEM

PCI based read-out receiver cardNEC2001, September, DDL C OMPONENTS  Destination Interface Unit (DIU)  Source Interface Unit (SIU)  Physical medium Multimode optical cable Maximum 200m long Front-End Electronics (FEE) Front-End Electronics (FEE) Source Interface Unit (SIU) Read-Out Receiver Card (RORC) Forward Channel Backward Channel DDL Hardware = Source Interface Unit + Physical Medium + Destination Interface Unit Physical Medium Destination Interface Unit (DIU) Read-out Receiver Card (RORC)

PCI based read-out receiver cardNEC2001, September, DDL R EQUIREMENTS  Bi-directional data transfer 100 MB/s from the detectors 10 MB/s to the detectors  Detected BER must be less than  Remote control capability FEE control SIU control  Detailed status and error reporting  Built in test capability  JTAG BST over the link FEE control and test

PCI based read-out receiver cardNEC2001, September, PCI RORC C ONCEPT  Interface between the DIU and PCI local bus 32bit/33Mhz PCI version, max. throughput 132MB/s  Direct data transfer to the PC memory No local memory on the board Small elasticity buffers between different clock domains  Data push architecture, PCI master operation Data transfer with minimal software interaction Minimize latency  Memory management Efficient for scattered memory management Minimize software overhead  Built-in test capability Internal pattern generator can produce quasi-realistic data

PCI based read-out receiver cardNEC2001, September, PCI RORC D EVELOPMENT 1/2 IMB OMB PCI to AOL FIFO AOL to PCI FIFO AOL interface Read DMA controller Write DMA controller Memory manager and command interpreter DIU interface Receiver FIFO Transmitter FIFO Pattern Generator PCIDIU pRORC firmware architecture AOL – Add-on Logic Output Mailbox Input Mailbox

PCI based read-out receiver cardNEC2001, September, BABLIDXBABLIDXBABLIDX PCI RORC D EVELOPMENT 2/2 BABLIDX RFBAIDX Free FIFO (128 entry) PC physical memory BA – Base Address BL – Block Length IDX – Ready FIFO Entry Index RFBA – Ready FIFO Base Address Ready FIFO Scattered Memory Management

PCI based read-out receiver cardNEC2001, September, PCI RORC P ERFORMANCE 1/2  Test firmware developed to test the DMA Fixed size block transferred (n Word) Simple test pattern used (without data check)  Test software controls the firmware and measures the performance Stand alone operation Base address Base address + 4 Block Counter Data buffer Base address + 4(n+1)

PCI based read-out receiver cardNEC2001, September, PCI RORC P ERFORMANCE 2/2  Same test firmware and software used  Additional software components Intensive memory usage (stream_l benchmarking tool) Intensive network usage (Gigabit Ethernet) Intensive CPU usage (stream_l + DATE 1 ) 1 DATE – Data Acquisition and Test Environment KB block size

PCI based read-out receiver cardNEC2001, September, S UMMARY  Results: 5 boards are available for prototyping Software drivers for 2.2.x and 2.4.x kernels Software library for integration with DAQ system  Future plans: Migrate to PCI 64bit/66MHz Implement on-board memory and pre-processing capabilities Develop WEB-based GUI

PCI based read-out receiver cardNEC2001, September,

PCI based read-out receiver cardNEC2001, September, PCI RORC B OARD

PCI based read-out receiver cardNEC2001, September, DDL DIU B OARD

PCI based read-out receiver cardNEC2001, September, DDL SIU B OARD