This material exempt per Department of Commerce license exception TSU Architecture Wizard and PACE Lab 2 Introduction.

Slides:



Advertisements
Similar presentations
INPUT-OUTPUT ORGANIZATION
Advertisements

EMS1EP Lecture 4 Intro to Programming Dr. Robert Ross.
8086 [2] Ahad. Internal! External? 8086 vs _bit Data Bus 20_bit Address 8_bit Data Bus 20_bit Address Only external bus of 8088 is.
Lab7: Introduction to Arduino
Dr A Sahu Dept of Computer Science & Engineering IIT Guwahati.
DATA COLLECTION USING ZIGBEE NETWORK Timothy Melton Moscow, ID.
1 Homework Reading –Review previous material on “interrupts” Machine Projects –MP4 Due today –Starting on MP5 (Due at start of Class 28) Labs –Continue.
RS-232 Port Discussion D7.1. Loop feedback RS-232 voltage levels: +5.5 V (logic 0) -5.5 V (logic 1)
Configurable System-on-Chip: Xilinx EDK
7-1 Digital Serial Input/Output Two basic approaches  Synchronous shared common clock signal all devices synchronised with the shared clock signal data.
Computer Organization and Assembly language
ECE Department: University of Massachusetts, Amherst Lab 1: Introduction to NIOS II Hardware Development.
v8.2 System Generator Audio Quick Start
1 Mid-term Presentation Implementation of generic interface To electronic components via USB2 Connection Supervisor Daniel Alkalay System architectures.
ASPPRATECH.
INPUT-OUTPUT ORGANIZATION
© 2011 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU Xilinx Tool Flow.
Khaled A. Al-Utaibi  8086 Pinout & Pin Functions  Minimum & Maximum Mode Operations  Microcomputer System Design  Minimum Mode.
Sept EE24C Digital Electronics Project Design of a Digital Alarm Clock.
Digilent System Board Capabilities Serial Port (RS-232) Parallel Port 1 Pushbutton Hint: Good for a reset button Connected to a clock input. See Digilent.
ISE. Tatjana Petrovic 249/982/22 ISE software tools ISE is Xilinx software design tools that concentrate on delivering you the most productivity available.
8254 Counter/Timer Counter Each of the three counter has 3 pins associated CLK: input clock frequency- 8 MHz OUT GATE: Enable (high) or disable.
Final presentation – part B Olga Liberman and Yoav Shvartz Advisor: Moshe Porian April 2013 S YMBOL G ENERATOR 2 semester project.
This material exempt per Department of Commerce license exception TSU Writing Basic Software Applications Lab 4 Introduction.
MICROPROCESSOR INPUT/OUTPUT
Unit 4 Design and Synthesis of Datapath Controllers
Microchip PIC Networks Amrit Bandy, Ben Funk Neil Goldsman.
Industrial Reference Design Platform RS-232 Interface Developed by the TSC Americas Release 1.0.
1 Lab 1: Introduction. 2 Configure ATMEL AVR Starter Kit 500 (STK500), a prototyping/development board for Lab1. ATmega16 ( V) is the chip used.
Forging new generations of engineers
Autonomous Helicopter James LydenEE 496Harris Okazaki.
ECE 448 – FPGA and ASIC Design with VHDL Lecture 12 PicoBlaze Overview.
Lab:How to use SSG to build your security solution V1.0 Bob Yi Aug 4, 2008.
This material exempt per Department of Commerce license exception TSU Xilinx Tool Flow.
Universal Asynchronous Receiver/Transmitter (UART)
1 EDK 7.1 Tutorial -- SystemACE and EthernetMAC on Avnet Virtex II pro Development Boards Chia-Tien Dan Lo Department of Computer Science University of.
ATtiny23131 A SEMINAR ON AVR MICROCONTROLLER ATtiny2313.
PROJECT - ZYNQ Yakir Peretz Idan Homri Semester - winter 2014 Duration - one semester.
Interrupt driven I/O. MIPS RISC Exception Mechanism The processor operates in The processor operates in user mode user mode kernel mode kernel mode Access.
Serial Communications Interface Module Slide #1 of 19 MC68HC908GP20 Training PURPOSE -To explain how to configure and use the Serial Communications Interface.
Part A Final Dor Obstbaum Kami Elbaz Advisor: Moshe Porian August 2012 FPGA S ETTING U SING F LASH.
Lab 2.
11 EENG 1920 Introduction to VHDL. 22 Hardware Description Language A computer language used to design circuits with text-based descriptions of the circuits.
Interrupt driven I/O Computer Organization and Assembly Language: Module 12.
CDA 4253 FPGA System Design The PicoBlaze Microcontroller
Teaching Digital Logic courses with Altera Technology
بسم الله الرحمن الرحيم MEMORY AND I/O.
The 8085 Microprocessor Architecture. What 8085 meant for? 80 - year of invention bit processor 5 - uses +5V for power.
Chapter Microcontroller
CDA 4253 FPGA System Design PicoBlaze Interface Hao Zheng Comp Sci & Eng U of South Florida.
SMS Based Industrial Automation Using ARM Controller Under the guidance of : Smt Jayanthi.K.Murthy Assistant Professor, PG Studies, Dept of E&C, BMSCE,
CDA 4253 FPGA System Design PicoBlaze Interface Hao Zheng Comp Sci & Eng U of South Florida.
Introduction to the FPGA and Labs
Maj Jeffrey Falkinburg Room 2E46E
The HCS12 SCI Subsystem A HCS12 device may have one or two serial communication interface. These two SCI interfaces are referred to as SCI0 and SCI1. The.
Homework Reading Machine Projects
Michael Rahaim, PhD Candidate Multimedia Communications Lab
Lab 1: Using NIOS II processor for code execution on FPGA
Source: Serial Port Source:
Lecture 15 PicoBlaze Overview
COMP2121: Microprocessors and Interfacing
Programmable Interval Timer
Homework Reading Machine Projects Labs
Getting Started with Programmable Logic
Lecture 14 PicoBlaze Overview
8254 Timer and Counter (8254 IC).
Lecture 16 PicoBlaze Overview
Founded in Silicon Valley in 1984
Source: Serial Port Source:
8253 – PROGRAMMABLE INTERVAL TIMER (PIT). What is a Timer? Timer is a specialized type of device that is used to measure timing intervals. Timers can.
Presentation transcript:

This material exempt per Department of Commerce license exception TSU Architecture Wizard and PACE Lab 2 Introduction

Lab 2 Intro 2 Introduction This lab guides you through the process of adding a DCM (Digital Clock Manager) into a PicoBlaze UART real-time clock design. – The DCM will divide the 100 MHz system clock on the XUP Virtex-II Pro board down to 50 MHz. – This 50 MHz will clock the design which consists of the PicoBlaze, TX and RX UARTs, and control logic. You will generate a bitstream and configure the Virtex-II Pro device on the XUP board – You will interact with PicoBlaze via hyperterminal to set the current and alarm times, and start and stop the times. – When the alarm goes off, an LED will flash.

Lab 2 Intro 3 Objectives After completing this module, you will be able to: Use architecture wizard to parameterize a DCM Instantiate the DCM into the design using the language template Specify pin constraints using PACE Download and test the design in hardware

Lab 2 Intro 4 General Flow Step 1: Use the architecture wizard to configure a DCM Step 2: Instantiate the DCM into a VHDL/Verilog design Step 3: Use PACE to assign pin locations Step 4: Verify PAD report and start a hyperterminal session Step 5: Download the Design Step 6: Operating the Real-Time UART clock

Lab 2 Intro 5 UART Real-Time Clock The design understands some simple ASCII commands – TIME – current time displayed according to 24 hour clock in format hh:mm:ss – TIME hh:mm:ss – allows time to be set according to 24 hour clock – ALARM – current alarm time will be displayed according to 24 hour clock. The current status of the alarm will be displayed (ON, OFF, Active) – ALARM hh:mm:ss – allows the alarm to be set according to the 24 hour clock. The new alarm time and current status will be displayed. – ALARM ON – Enables the alarm to be active. Current alarm time and status will be displayed. – ALARM OFF – Disables the alarm. Current alarm time and status will be displayed

Lab 2 Intro 6 PicoBlaze Hardware Design PicoBlaze uart_tx Instructions Address Instructions rx_data out_port[7:0] port_id[7:0] write_strobe D Q en port_id[0] Interrupt_ack alarm tx interrupt control Interrupt_event DCM clk 100 MHz 50 MHz D Q en uart_rx rx rx_data tx_full, tx_half_full rx_half_full rx_full 000 Baud Count en_16_x_baud You will add the DCM to the design

Lab 2 Intro 7 Basic Overview of Source Input port definition For PicoBlaze Output port definition For PicoBlaze Register Names

Lab 2 Intro 8 Basic Overview of Source Initialization Prompt user for input, Checking for “TIME” Or “ALARM” Checks to see if “TIME” Is entered correctly; Also Checks to see if a command Was entered Current time entered by user is tested, stored in PicoBlaze registers, and Transmitted to the UART for display On hyperterminal

Lab 2 Intro 9 Basic Overview of Source Checks to see if “ALARM” Is entered correctly; Also Checks to see if a command Is entered Alarm time command entered by user is tested. If an alarm time is entered, it is stored in PicoBlaze registers, and Transmitted to the UART for display on hyperterminal