EKT 221 : Digital 2 Serial Transfers & Microoperations Date : Lecture : 2 hr

Serial Transfers & Microoperations Serial transfers Serial transfers –Used for “narrow” transfer paths –Example : Telephone or cable line  Parallel – to – Serial : at source  Serial – to – Parallel : at destination Serial micro-operations Serial micro-operations –Example 1 : Addition –Example 2 : Error – Correction for CDs Parallel  Serial Serial  Parallel SourceDestination

Serial Transfers Serial mode  info is transferred / manipulated one bit at a time Serial mode  info is transferred / manipulated one bit at a time Serial transfer from RA to RB is done with shift registers Serial transfer from RA to RB is done with shift registers

Serial Transfers Serial output (SO) of A connected with serial input (SI) of B Serial output (SO) of A connected with serial input (SI) of B SI of A receives 0’s SI of A receives 0’s Data from A transferred to B Data from A transferred to B Initial content of B shifted out to SO of B and lost Initial content of B shifted out to SO of B and lost

Serial Transfers To maintain the data in A, connect SO of A to its SI To maintain the data in A, connect SO of A to its SI

Serial Transfers Shift  determine when & how many times the registers are shifted Shift  determine when & how many times the registers are shifted Clock pulse (Clock) can pass to C only when Shift is HIGH (1) Clock pulse (Clock) can pass to C only when Shift is HIGH (1)

Serial Transfers

Serial Micro-operations Serial addition is a low cost way to add large numbers of operands, since a “tree” of full adder cells can be made to any depth. Serial addition is a low cost way to add large numbers of operands, since a “tree” of full adder cells can be made to any depth. Other operations can be performed serially as well, such as parity generation / checking or more complex error – check codes. Other operations can be performed serially as well, such as parity generation / checking or more complex error – check codes. Shifting a binary number left = multiplying by 2 Shifting a binary number left = multiplying by 2 –E.g sl 0100  1000 Shifting a binary number right = dividing by 2 Shifting a binary number right = dividing by 2 –E.g sr 0100  0010

Serial Adder The circuit shown uses 2 shift registers for operands The circuit shown uses 2 shift registers for operands –A (3 :0) –B (3:0) A full adder, and one more FF (for carry) is used to compute the sum A full adder, and one more FF (for carry) is used to compute the sum Result stored in A register and final carry in FF Result stored in A register and final carry in FF

Serial Adder SI of B can receive new inputs SI of B can receive new inputs In each clock pulse / cycle : In each clock pulse / cycle : –New sum bit is transferred to A –New carry transferred to FF –Both registers shifted once to the right –Process cont. until Shift = 0

Analyzing the circuit : Serial Adder A3A2A1A0B3B2B1B0 SUM (A+B) + Cin CoutCinT T1 T2 T3 T4 Example 1: Reg A : 1000 Reg B : 0101

Analyzing the circuit : Serial Adder A3A2A1A0B3B2B1B0 SUM (A+B) + Cin CoutCinT T T T T ANSWER : 1101, after 4 clock cycle

Analyzing the circuit : Serial Adder A3A2A1A0B3B2B1B0 SUM (A+B) + Cin CoutCinT T1 T2 T3 T4 Example 2: Reg A : 1011 Reg B : 0101

Analyzing the circuit : Serial Adder A3A2A1A0B3B2B1B0 SUM (A+B) + Cin CoutCinT T T T T ANSWER : 10000, after 4 clock cycle 1 is indicated in Cout

Parallel Adder FA A0 B0 Cin FA A1 B1 FA A2 B2 FA A3 B3 Cout S0 S1 S2 S3 Reg A Sin Sout A0 A1 A2 A3 Reg B Sin Sout B0 B1 B2 B3 Can be the input for Reg A

Serial Vs Parallel Transfers Space Vs Time Trade-off Space Vs Time Trade-off Serial adder is a seq. cct because it includes the carry from FF. but need n clock cycle to complete the addition (Less Space, more Time) Serial adder is a seq. cct because it includes the carry from FF. but need n clock cycle to complete the addition (Less Space, more Time) Parallel adder is a comb. cct because it needs n FA for n bit operation. Need only one clock cycle to complete the addition. (More Space, less Time) Parallel adder is a comb. cct because it needs n FA for n bit operation. Need only one clock cycle to complete the addition. (More Space, less Time) Gives the designer choice. Gives the designer choice. –More Space – More cost –More Time – More delay (not fast)

Thank You